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Author Topic: Klondike - 16 chip ASIC Open Source Board - Preliminary  (Read 434701 times)
BkkCoins
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May 04, 2013, 11:27:23 AM
 #141

Here's a teaser. I've done just about as much as I can for the moment.
I could tidy it up a bit and make some bits more pretty.

If I recall correctly this is the top and bottom layers with solder paste.
The middle layers aren't shown. Note that data signals will be on a middle layer.

And I'm still playing with the connector area. I may put pads for an SMD barrel jack at board edge next to PCIe power so that those who want no thru holes (due to heat sink) can use that. I could find no SMD mount PCIe connectors so best bet there is to drill the heat sink or put copper pads between it and the board. Kind of a nuisance really.

I should have changed the name of that silly 1PIN hole footprint.


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May 04, 2013, 11:40:55 AM
 #142

Has anyone taken apart an ASIC they bought? To like, reverse engineer?

What is keeping this project from completing?

Really? Do you know how many ASICs there are out there now?
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May 04, 2013, 11:44:39 AM
 #143

Here's a teaser. I've done just about as much as I can for the moment.
I could tidy it up a bit and make some bits more pretty.

If I recall correctly this is the top and bottom layers with solder paste.
The middle layers aren't shown. Note that data signals will be on a middle layer.

And I'm still playing with the connector area. I may put pads for an SMD barrel jack at board edge next to PCIe power so that those who want no thru holes (due to heat sink) can use that. I could find no SMD mount PCIe connectors so best bet there is to drill the heat sink or put copper pads between it and the board. Kind of a nuisance really.

I should have changed the name of that silly 1PIN hole footprint.



Nice frisbee... woot. Can't wait to either make em or get them chips mated to them.

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May 04, 2013, 12:09:59 PM
 #144

Here's a teaser. I've done just about as much as I can for the moment.
I could tidy it up a bit and make some bits more pretty.

If I recall correctly this is the top and bottom layers with solder paste.
The middle layers aren't shown. Note that data signals will be on a middle layer.

And I'm still playing with the connector area. I may put pads for an SMD barrel jack at board edge next to PCIe power so that those who want no thru holes (due to heat sink) can use that. I could find no SMD mount PCIe connectors so best bet there is to drill the heat sink or put copper pads between it and the board. Kind of a nuisance really.

I should have changed the name of that silly 1PIN hole footprint.


I love it! :-)

4x4 thermal vias under each asic, nice!
Heatsink-holes, usable for aligning the stencil? Great!

I would love an smd barrel-jack! There seems to be some space left free left of the pci-e powerconnector?
If the pci-e powerconnector isn't populated, do you think the solderpoints would short on a flat heatsink? The soldermask adds some tiny space, and ignoring the thermal compound and oxide layer in between too.

All in all there seems to be quite some space unused. Of course the other layers are not visible here, though. Considering the original avalon module is 37mm wide (for 10 chips only)..
Nah, ignore that, you know what you're doing, BKKCoins! :-)

To repeat: I love it! :-)

edit:
About aligning:
The solder pads are tiny. What do you guys think, would the holes be positioned precisely enough to align the stencil with them? That would help a lot! If we can define a narrower tolerance for the (4 corner) holes I would gladly pay extra.

Oh, and +1 for larger physical capacitor size etc ;-)

Ente
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May 04, 2013, 01:32:00 PM
 #145

This one shows holes and heat sink pads under the thermal vias. It's the bottom mask - areas of exposed copper. The thermal pads are 1cm square. I forget now the hole diameter, maybe 4mm but if there is a good standard size let me know. (Don't measure here as this includes a ring around the hole)



I would love an smd barrel-jack! There seems to be some space left free left of the pci-e powerconnector?
If the pci-e powerconnector isn't populated, do you think the solderpoints would short on a flat heatsink? The soldermask adds some tiny space, and ignoring the thermal compound and oxide layer in between too.

edit:
About aligning:
The solder pads are tiny. What do you guys think, would the holes be positioned precisely enough to align the stencil with them? That would help a lot! If we can define a narrower tolerance for the (4 corner) holes I would gladly pay extra.
Yes, planned for barrel jack in space behind PCIe. Probably a couple decent sized pads there that could even just be soldered to, or other connectors could use. I have a datasheet for a 4UCON SMD barrel jack and also a Switchcraft one is available at Mouser for 8x the price.

With a flat heatsink it would likely be best to put some suitable tape over unpopulated holes just to be safe. Or if some thermal pads are used under the ASICs the heat sink may stand off enough. We'll have to see.

You may be able to register to the holes. There is a known tolerance on them but generally I've stuck down the stencil to something holding the board so it's to the board edge. You'll need to visually inspect, and it isn't hyper critical as the solder paste can even be messy and it'll pull into place due to surface tension and the mask preventing it going elsewhere.

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May 04, 2013, 02:39:06 PM
 #146

This one shows holes and heat sink pads under the thermal vias. It's the bottom mask - areas of exposed copper. The thermal pads are 1cm square. I forget now the hole diameter, maybe 4mm but if there is a good standard size let me know. (Don't measure here as this includes a ring around the hole)

http://i.imgur.com/zMSgPvm.png

BkkCoins this article has a nice table of thermal resistance reduction for different vias arrays that can serve you as a reference their model uses a 10mm square die vs the 7mm Avalon chips has.
 
http://www.electronics-cooling.com/2004/08/thermal-vias-a-packaging-engineers-best-friend/

Abrazos,
Dieguito
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May 04, 2013, 03:42:11 PM
 #147

BkkCoins this article has a nice table of thermal resistance reduction for different vias arrays that can serve you as a reference their model uses a 10mm square die vs the 7mm Avalon chips has.
 
http://www.electronics-cooling.com/2004/08/thermal-vias-a-packaging-engineers-best-friend/

Abrazos,
Dieguito
Thank you. I actually saw that article when looking for information on what spacing and how many to use. I came across an industry forum post that discussed the spacing based on past board experience where 1.5mm was indicated as a good value. I thought about using 5 or 6 rows/cols as that would be maximal in line with the first article for a 7mm chip. 1.5mm spacing on a 10mm die would be about 7x7 equivalent, 85% reduction in resistance.

I figure it would take me an hour to revise them to smaller spacing at 5x5 or 6x6, and I may yet do that if information turns up that it would work much better. I believe there is a limit to via count on board production as well, and from what I recall even 6x6 wouldn't push past that. What held me back was thinking that too many holes would weaken the board structure. My fab has a 0.3mm minimum drill size so I can't make the holes smaller when spacing closer. With laser vias you can make smaller holes on much closer spacing. That would also push up the board cost considerably as I read they charge by the hole.




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May 04, 2013, 05:03:09 PM
 #148

Here's a teaser. I've done just about as much as I can for the moment.
I could tidy it up a bit and make some bits more pretty.

If I recall correctly this is the top and bottom layers with solder paste.
The middle layers aren't shown. Note that data signals will be on a middle layer.

And I'm still playing with the connector area. I may put pads for an SMD barrel jack at board edge next to PCIe power so that those who want no thru holes (due to heat sink) can use that. I could find no SMD mount PCIe connectors so best bet there is to drill the heat sink or put copper pads between it and the board. Kind of a nuisance really.

I should have changed the name of that silly 1PIN hole footprint.


If you can, i'd recommend adding fiducial markers on the silkscreen, both a few on the corners of the board, and local ones by each QFN [dot by pin 1].  for the board ones you can do a circle of copper on the top layer (with no soldermask) as well

Also i've been reading a few design notes on QFN heatsinking - it might be worth using 2 or even 3oz copper on the internal ground plane for added heat conduction, but i need to do some testing more more reading - just something to be aware of

How are you doing the layer stackup?  Which layer is the power/ground plane?
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May 04, 2013, 07:24:52 PM
 #149

Hi
BkkCoins, looks realy good project.
For power you consider a jack 3'5mm?

I'm from spain two days ago I contacted with some assembly factory here in barcelona.

Considering the quantity to make for spanish, french users in forum to make a group assembly.

We are in contact.

Regards Smiley

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May 04, 2013, 07:27:37 PM
 #150

I would suggest a higher density of vias for the thermal pad. Here is an example of ones that we do for power drivers.

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May 04, 2013, 07:31:31 PM
 #151

Both a barrel jack and a Molex pcie power connector may be a good option. For those who wish to power this as a separate unit instead of housing a bunch and running them off an ATX power supply.

I would consider a right angle Molex PCIe connector.

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May 04, 2013, 10:29:15 PM
Last edit: May 04, 2013, 10:46:38 PM by ecliptic
 #152

I would suggest a higher density of vias for the thermal pad. Here is an example of ones that we do for power drivers.


Definitely if possible, but there's a diminishing return for # of vias though, something around 12-14 vias for a 7x7mm QFN.  Going to say 25 might only be a 10% increase

I'll try to put together some links to design guides on these and thermal analysis.

It would be very nice if we could vary the clock and core voltage in case some of the chips have a worse thermal resistance than others and heat up -- mostly for DIY people who will get inconsistent reflow between the thermal pad and the PCB.  they could at least declock and/or de-volt the QFNs so they don't burn themselves up.

better to have 50% output performance than 0%.
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May 04, 2013, 11:07:17 PM
 #153

I didn't see a thermistor in the BOM for the board temperature.

For that we need:

Thermistor   TFPT1206L4701FM   Vishay-Dale   4.7K 1%   1206
Thick Film Resistor   CRCW060310K0JNEA   Vishay-Dale   10K 5%   0603
Thick Film Resistor   CRCW06031K00JNEA   Vishay-Dale   1K 5%   0603
Ceramic Capacitor   GRM188R61C104KA01D   Murata   0.1uF   0603
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May 05, 2013, 12:22:42 AM
 #154

Both a barrel jack and a Molex pcie power connector may be a good option. For those who wish to power this as a separate unit instead of housing a bunch and running them off an ATX power supply.

I would consider a right angle Molex PCIe connector.
The PCIe is placed at the correct distance in from board edge so that either a right or straight connector will work.

I would suggest a higher density of vias for the thermal pad. Here is an example of ones that we do for power drivers.
I could easily increase it and I may still. My brief research indicated 1.5mm spacing as optimal. It may be worth spending $10 for test boards with 15,25,36 via pads and a bundle of 1/2W resistors placed around the pad body to simulate, before ordering final boards. Or with the prototype board use one bank of 16 and one of 25 to test difference.

If you can, i'd recommend adding fiducial markers on the silkscreen, both a few on the corners of the board, and local ones by each QFN [dot by pin 1].  for the board ones you can do a circle of copper on the top layer (with no soldermask) as well

Also i've been reading a few design notes on QFN heatsinking - it might be worth using 2 or even 3oz copper on the internal ground plane for added heat conduction, but i need to do some testing more more reading - just something to be aware of

How are you doing the layer stackup?  Which layer is the power/ground plane?
Definitely plan to add and the silkscreen now is just what Kicad did by default. I haven't looked at it yet for adding what I want and removing garbage like "PIN1".

I was working with a rather basic 1.6mm stack:

top 1.2V plane, 1oz
0.2 FR4
inner 1 3.3V plane, 0.5oz
1.2 FR4
inner 2 signal, 0.5oz
0.2 FR4
bottom GND plane, 1oz

But there is more GND planes under the switching supply, and a few signals escape on inner 1.

I'm open to suggestions but something unusual will push the board cost up. Part of keeping the cost down is that they batch with other boards, so go weird and it will likely push cost by 5-10x or more (for short runs anyway). I'd consider using a thin board to help heat pass to the back more easily and I can go 1.2mm total for the same cost. I'm just unsure of the downside to that.

I didn't see a thermistor in the BOM for the board temperature.
I'm using the temperature sensor built in to the PIC chip. It's not located under an ASIC die but then we can't have 16 sensors anyway, and this should be some average being close to one end of the board. I think it will be enough to calibrate a temp/fan speed relationship but obviously not an accurate die temp reading.


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May 05, 2013, 01:39:45 AM
 #155

I would suggest a higher density of vias for the thermal pad. Here is an example of ones that we do for power drivers.
I could easily increase it and I may still. My brief research indicated 1.5mm spacing as optimal. It may be worth spending $10 for test boards with 15,25,36 via pads and a bundle of 1/2W resistors placed around the pad body to simulate, before ordering final boards. Or with the prototype board use one bank of 16 and one of 25 to test difference.

If you can, i'd recommend adding fiducial markers on the silkscreen, both a few on the corners of the board, and local ones by each QFN [dot by pin 1].  for the board ones you can do a circle of copper on the top layer (with no soldermask) as well

Also i've been reading a few design notes on QFN heatsinking - it might be worth using 2 or even 3oz copper on the internal ground plane for added heat conduction, but i need to do some testing more more reading - just something to be aware of

How are you doing the layer stackup?  Which layer is the power/ground plane?
Definitely plan to add and the silkscreen now is just what Kicad did by default. I haven't looked at it yet for adding what I want and removing garbage like "PIN1".

I was working with a rather basic 1.6mm stack:

top 1.2V plane, 1oz
0.2 FR4
inner 1 3.3V plane, 0.5oz
1.2 FR4
inner 2 signal, 0.5oz
0.2 FR4
bottom GND plane, 1oz

But there is more GND planes under the switching supply, and a few signals escape on inner 1.

I'm open to suggestions but something unusual will push the board cost up. Part of keeping the cost down is that they batch with other boards, so go weird and it will likely push cost by 5-10x or more (for short runs anyway). I'd consider using a thin board to help heat pass to the back more easily and I can go 1.2mm total for the same cost. I'm just unsure of the downside to that.

What do you mean spend 10$ for test boards?  The setup cost is usually several hundred dollars.

also, any reason you don't have an internal ground plane?  I'm only familar with a 4 layer, 1 Vcc, 1 Gnd setup, where typically the signals are routed on the top and bottom only if at all possible, and the middle two layers are reserved for ground and power.  The unused portions of the bottom layer can then be flooded with ground plane as well to facilitate heat transfer, especially around the QFN.  the top layer can be flooded with the 1.2V plane or mini-planes

I think it may be very important to have internal ground plane that the QFN is directly connected to.
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May 05, 2013, 01:49:27 AM
 #156

You can put the thermistor circuit in copper. Populate it on the test board and compare them. I'm working on a project now where we found the temp sensor in the micro to be wildly inaccurate. We had to go with a discrete circuit instead.

If we find the micro to be accurate enough we don't have to populate the external circuit.
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May 05, 2013, 01:52:11 AM
 #157


I could easily increase it and I may still. My brief research indicated 1.5mm spacing as optimal. It may be worth spending $10 for test boards with 15,25,36 via pads and a bundle of 1/2W resistors placed around the pad body to simulate, before ordering final boards. Or with the prototype board use one bank of 16 and one of 25 to test difference.

I just read a paper from TI recommending 1.0mm spacing.
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May 05, 2013, 02:02:23 AM
 #158

What do you mean spend 10$ for test boards?  The setup cost is usually several hundred dollars.

also, any reason you don't have an internal ground plane?  I'm only familar with a 4 layer, 1 Vcc, 1 Gnd setup, where typically the signals are routed on the top and bottom only if at all possible, and the middle two layers are reserved for ground and power.  The unused portions of the bottom layer can then be flooded with ground plane as well to facilitate heat transfer, especially around the QFN.  the top layer can be flooded with the 1.2V plane or mini-planes

I think it may be very important to have internal ground plane that the QFN is directly connected to.
I can order 10pcs, 5cm x 5cm boards for $10 plus shipping. But if I throw in some more stuff the the shipping is free. Min. $50 order for free shpg. From China.

I guess originally I had the GND on the bottom as I'd planned to have an open surface for maximum heat sink contact, but later I changed to just having pads for the heat contact and then never revisited moving the GND inside. The internal signal layer will actually have very few traces and will be flooded with GND as well, so it should achieve the same thing even though I haven't called it that. It does now seem an advantage to have the signals visible on the bottom so I could change that.

You can put the thermistor circuit in copper. Populate it on the test board and compare them. I'm working on a project now where we found the temp sensor in the micro to be wildly inaccurate. We had to go with a discrete circuit instead.

If we find the micro to be accurate enough we don't have to populate the external circuit.
Not a bad idea. Will look at that.

I just read a paper from TI recommending 1.0mm spacing.
Do you have a reference for that so I can read up more?




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May 05, 2013, 02:07:18 AM
 #159

http://www.cirrus.com/en/pubs/appNote/AN315REV1.pdf

- Note the significant decrease in temperature when going from 1oz copper to 2oz or possibly even 3oz copper on the internal plane (page 10)

half oz copper for the internal plane (if used for heatsinking) is bad

http://www.ti.com/lit/an/sloa122/sloa122.pdf

http://www.freescale.com/files/analog/doc/app_note/AN1902.pdf

http://www.onsemi.com/pub_link/Collateral/AND8432-D.PDF

Also - can i ask who you get the 10$ PCBs from?
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May 05, 2013, 03:43:20 AM
 #160

The 1/2oz layer is not for heatsinking.
The pad under the ASIC is a ground pad the heat transfers thru the 16 via to the bottom ground plane.

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