Modular FPGA Miner Hardware Design Development

[Olaf.Mandel]

I don't want to kill the project via feature-creep, but if the chips can be individually be brought up via USB, can they be shut-down as well?
[...]

A resounding "yes". [...]

Maybe I should be more careful: as individual boards, the complete board can be brought up/down at will. You wouldn't be able to address the power of individual FPGAs on one board, though. And if plugged into a backplane, I would have to think a bit first if one board can be powered down without problems for the rest (mostly a question of how the level shifters behave is half off and of giving each slot an individual enable-power signal).

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[BkkCoins]

Is that even needed? Wouldn't it be possible to load an FPGA configuration that sets it in a sleep state using almost no power? Nothing connected to anything or in tri-state mode.

[Olaf.Mandel]

Is that even needed? Wouldn't it be possible to load an FPGA configuration that sets it in a sleep state using almost no power? Nothing connected to anything or in tri-state mode.

Go one better: reset the complete device and do not load a new bitpattern. This will keep at least the Xilinx devices at their lowest power consumption short of disabling the power supply. For a XC6SLX150, the quiescent currents you get are given in DS162 (DC and Switching Characteristics): a total of 109mW over 1.2V and 2.5V.

So yes, power supply disabling is one extra pin needed on the USB interface chip, but what can it hurt?

[BkkCoins]

I would expect that can be done via JTAG as well.

[phillipsjk]

I haven't looked at the specs, but don't most chips require the interface pins to be held below the supply voltage? I am concerned that if you bring down one board, you may bring down all the boards using the same back-plane. Using the USB interface as a buffer should work though.

[Olaf.Mandel]

I would expect that can be done via JTAG as well.

I meant a USB interface pin connected to the power supplies remote enable pin, not to the FPGA reset pin. My argument was that 110mW (plus power supply losses!) are too much to justify using the reset state as a sleep mode alternative.

[Olaf.Mandel]

I haven't looked at the specs, but don't most chips require the interface pins to be held below the supply voltage? I am concerned that if you bring down one board, you may bring down all the boards using the same back-plane. Using the USB interface as a buffer should work though.

Actually, as we want to keep the bus open for different FPGAs, we probably cannot specify a signalling voltage that is directly compatible to out FPGA. Instead, we will probably use a different voltage and require all DIMMs to include level shifters to the FPGA voltage. These level shifters would then protect the powered-down DIMMs, because only their FPGA-facing supply voltage is missing. Their bus-facing supply voltage would still be supplied by the bus, so they would be fine. It is a good point, though: we need to carefully read the datasheet of any IC we put on the DIMMs.

[makomk]

Actually, as we want to keep the bus open for different FPGAs, we probably cannot specify a signalling voltage that is directly compatible to out FPGA. Instead, we will probably use a different voltage and require all DIMMs to include level shifters to the FPGA voltage. These level shifters would then protect the powered-down DIMMs, because only their FPGA-facing supply voltage is missing. Their bus-facing supply voltage would still be supplied by the bus, so they would be fine. It is a good point, though: we need to carefully read the datasheet of any IC we put on the DIMMs.

Most FPGAs are fairly flexible about what signalling voltages you can set them up for, from what I've seen.

Edit: Also, I'm pretty sure the ones we're likely to want to use are meant to be OK with in-spec voltages on their I/O pins whilst powered down.

[O_Shovah]

A little update from m side.

I've wrote to Xilinx and Altera, asking if we could find solutions for the problem concering the payware ISE needed for the Sp6 Lx150 and the altera software.
But ive gotten no response yet. Seems i will have to wait till monday.

Maybe to make this clear.

Wich FPGA's are at maximum supported by the free variants of the software for programming respectivley by Altera and Ximlinx so which would be our fall back solutions ?     Just in case

[makomk]

A little update from m side.

I've wrote to Xilinx and Altera, asking if we could find solutions for the problem concering the payware ISE needed for the Sp6 Lx150 and the altera software.
But ive gotten no response yet. Seems i will have to wait till monday.

Maybe to make this clear.

Wich FPGA's are at maximum supported by the free variants of the software for programming respectivley by Altera and Ximlinx so which would be our fall back solutions ?     Just in case

For Xilinx, biggest supported Spartan-6 is the XC6SLX75 and 75T (and possibly the equivalent Virtex-6), biggest full-stop is the prohibitively expensive Kintex XC7K160T. I think that Altera's free tools support all Cyclone III/IV FPGAs, and Stratix III support tops out at the EP3SL70.

(Also, my latest attempt to cram a fully-unrolled miner onto the XC6SLX75 just failed place and route. No surprises there...)

Edit: Either I'm hallucinating or this tweaked fully-unrolled miner just completed synthesis for the XC6SLX75. At a uselessly low clock frequency, true, but still...

[TheSeven]

Can you send me that design? I'd like to validate it. I even failed with a singly-unrolled one on an LX100.
Nevertheless, even if it would run at 100MHz, that would probably not be worth it. Doubly-unrolled should be more efficient, as the price difference between LX75 an LX150 is way less than a factor of 2.

[makomk]

Can you send me that design? I'd like to validate it. I even failed with a singly-unrolled one on an LX100.
Nevertheless, even if it would run at 100MHz, that would probably not be worth it. Doubly-unrolled should be more efficient, as the price difference between LX75 an LX150 is way less than a factor of 2.

Hopefully this archive should have all the bits you need. It won't actually run like that, because there are no pin assignments and the PLL speed setting is all wrong, but with a bit of luck you should be able to coax it into doing something. Unfortunately it's rather dependent on the right build settings, and I'm not even sure if they've copied over from SmartXplorer properly, let alone to that archive.

Edit: Oh, and don't try changing LOOP_LOG2 from 0 with that code; it won't work correctly.

[O_Shovah]

Doubly-unrolled should be more efficient, as the price difference between LX75 an LX150 is way less than a factor of 2.

I  would love to use the Lx150 if it is possible.But i found a quote that the full size Xilinx software needed for it would be around 2000 $ a year.
If a (expensive) payware is needed for programming and running the FPGA, it would certainly kill the idea of the open source Miner plattform open to everyone .

Maybe someone could try to verify the price for the software needed for using the SP6 LX150.A rate for it less than 100 € or similar might be bearable.

[lame.duck]

This software is only needed for generating the bitstream, in theory it would be sufficient to have somebody  generating the bitstream for you, but i don't know how much such a service would cost.

If you are a student you could also try out the CS oder EE laboratory

[TheSeven]

This software is only needed for generating the bitstream, in theory it would be sufficient to have somebody  generating the bitstream for you, but i don't know how much such a service would cost.

If you are a student you could also try out the CS oder EE laboratory

I'm sure that someone in the community would love to set up such a service, where you upload your design, get back the bitstream a couple of hours later if it succeeded, and pay per processing time. This kind of FPGA synthesis pool would make sense anyway, as you probably won't want to run SmartXPlorer on a single machine of your own and wait for days until you have a reasonably-optimized design. Parallelizing this and pooling it to increase usage/efficiency certainly makes sense.

[makomk]

I'm sure that someone in the community would love to set up such a service, where you upload your design, get back the bitstream a couple of hours later if it succeeded, and pay per processing time. This kind of FPGA synthesis pool would make sense anyway, as you probably won't want to run SmartXPlorer on a single machine of your own and wait for days until you have a reasonably-optimized design. Parallelizing this and pooling it to increase usage/efficiency certainly makes sense.

There's already a company called Plunify that's in the process of setting up exactly this service. Last I heard, Xilinx were being annoying about licensing though - they won't even let them offer the free WebPack functionality, let alone anything more powerful.

[markm]

Then don't offer such a service.

Keep it as an in-house capability useable only by employees and maybe shareholders of the GLBSE-listed concern that owns the license.

-MarkM- (P.S. no maybe about it, shareholders are owners so it is theirs to use...)

P.P.S. No, wait, maybe current owner doesn't want to donate/sell it to the concern. Can employees use their copy at work?

[phillipsjk]

I don't suppose the rules for generating a bitstream are documented?

I don't think it is exactly rocket science. It would be of comparable difficulty to writing a compiler. Obviously from the CPU time used, these tools brute force many possibilities.

[markm]

Brute force? What kind of brute force? GPU-amenable brute force?

-MarkM-

[phillipsjk]

It is probably an NP-Hard problem like the traveling salesman problem. The Software has to decide which traces to place where to get the shortest routing (allowing higher clock speeds). If lots of forking is involved, CPUs may be better at it (I don't know).

I don't think I have heard of GPU-accelerated compilers yet.