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Author Topic: PAPA ASIC  (Read 2452 times)
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papamoi (OP)
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December 13, 2013, 02:44:41 AM
Last edit: December 13, 2013, 05:08:59 AM by papamoi
 #1

HEY MODERATORS

STOP DELETING AND MOVING THIS THREAD

THANKS


Hi guys

after receiving accurate quotes from my ic house(chipmotion) based in shanghai china



here s what we ll have for our asic:

0.7/0.8 gigahash/chip
QFN package
65 nm tech
around 1w/giga of consumption

our fab will be SMIC .

As explained previously the gds is ready but we need to fund the tapeout and order a minimum wafer to get chips at cheapest cost possible.

For being able to give everyone 1Terrahash of chips we ll need 1400 chips/investor.

For being able to give these chips at cost price to everyone who will be with us on this venture,we ll need to have 1100 btc or 1.1 million usd
(1btc=1000 usd)

Each investor will get 1400 chips for 1.5 btc

so basically you ll get 1 th chip for 1500 us

and we need 735 investors who will invest 1.5 btc each

As i ll put my own 100k in this ,my shares in this will be 64 so we ll need now 671 investors bringing 1.50 btc each to get this done.

this is the adress where to send:

16VKxHkM8FHnAbyMPvu24QHDRxwCKKzh2n

send your name,email adress and adress with the transactions reference to btccashcom@gmail.com

feel free to pm me

remember minimum is 1.5 btc and you could always send a multiple of 1.5



the layout was already posted in my previous posts, i ll have the accurate chip details so we can start work on the pcb.

Please participate as this is an opportunity to get chips at cost price as you can do your math i won t earn 1 btc in this

thanks

P.s:my ignore list have plenty of rooms for trolls and other rats and smart arses
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December 13, 2013, 04:22:55 AM
 #2

You might want to include at least a basic timeline as everybody knows schedule is king in bitcoin mining...
papamoi (OP)
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December 13, 2013, 04:27:44 AM
 #3

You might want to include at least a basic timeline as everybody knows schedule is king in bitcoin mining...

timing is completely depending on the funds

so it s really difficult to write any date ,i just can say that if we have the funds now we can have the chips in less then 2 months

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December 13, 2013, 05:25:16 AM
 #4

I ve for got to add that the chip specs (for pcb design and else)are available on this link

https://drive.google.com/folderview?id=0B_EsXcAbNyswS1JFZ19XeTdfWUk&usp=sharing

People who wants to access it can drop me an email @ btccashcom@gmail.com with their bitcointalk id


these documents should not be posted elsewhere

thanks
papamoi (OP)
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December 13, 2013, 07:16:40 PM
 #5

Guys,

Please send me your bitcointalk id with the docs requests

thanks
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December 13, 2013, 10:24:57 PM
 #6

Hi,
You say the guys have sample proto-chips and it has been tested?

Can you post their formal report and some die photos

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papamoi (OP)
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December 14, 2013, 05:00:33 AM
Last edit: December 14, 2013, 05:24:46 AM by papamoi
 #7

Hi,
You say the guys have sample proto-chips and it has been tested?

Can you post their formal report and some die photos

we have some photos wich can be accessed on requests see above

there should be others tests and we ll post them as soon as we get something to post

thanks
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December 14, 2013, 05:14:03 AM
 #8

Sample prototype-chips as in FPGA right?
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December 14, 2013, 05:17:07 AM
 #9

Sample prototype-chips as in FPGA right?

No they look like sample asic chips.

Message me if you have any problems
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December 14, 2013, 05:23:37 AM
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Reserved
plasmoske
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December 14, 2013, 06:33:11 AM
 #11

Sample prototype-chips as in FPGA right?

No they look like sample asic chips.

How do you get sample ASIC chips when tapeout/wafers ain't even done yet?
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December 15, 2013, 09:45:04 PM
 #12

Reserved

What is the point of "Reserved" posts?

Sample prototype-chips as in FPGA right?

No they look like sample asic chips.

How do you get sample ASIC chips when tapeout/wafers ain't even done yet?
MPW
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December 16, 2013, 09:33:13 AM
 #13

hi guys

we ll have some video and sme pictures of the test chips

i hope this will permit us to finalize this project


thanks
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December 17, 2013, 05:07:53 AM
 #14

we have some photos wich can be accessed on requests see above

Why not post the photos for everyone to see?

How do you get sample ASIC chips when tapeout/wafers ain't even done yet?

I assume they were done in a MPW.

May I suggest that you include a provision to refund all investors if the funding goal is not met by some date (say March 16 2014, 3 months from now)?

"All safe deposit boxes in banks or financial institutions have been sealed... and may only be opened in the presence of an agent of the I.R.S." - President F.D. Roosevelt, 1933
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December 17, 2013, 05:14:07 AM
Last edit: December 17, 2013, 05:32:10 AM by papamoi
 #15

hi

it s easier for me to do this way regarding the docs and pictures

yes of course i ve posted it in other posts if we can t achieve the financing ,we ll return the funds

again people of the forum knows me enough that i m man of my words and i m not here to cheat or scam anyone

thanks
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December 17, 2013, 05:27:15 AM
 #16

Will you be making any of your in-hand sample chips available to board developers?

"All safe deposit boxes in banks or financial institutions have been sealed... and may only be opened in the presence of an agent of the I.R.S." - President F.D. Roosevelt, 1933
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December 17, 2013, 05:32:41 AM
 #17

Will you be making any of your in-hand sample chips available to board developers?

yes of course
papamoi (OP)
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December 21, 2013, 07:55:26 PM
 #18

hi guys

people who have access to the docs can see the new uploaded pictures of the test chips


tests are not complete yet

we ll post more progressively
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