Project Evil Genius – Custom SHA2-256 Circuits on a FPGA

[goxed]

Okay got it. Sometimes the synthesis software can also do logic optimization, which could reduce the size of hardware, though it's very rarely succesful in substantiial reduction of hand optimized designs.

[1713563196]

1713563196

[1713563196]

1713563196

[1713563196]

1713563196

[1713563196]

1713563196

[1713563196]

1713563196

[kramble]

why don't you try developing scrypt mining for LTC for opensource community. There's avery high demand for it IMO.

Jasinlee has a project running at http://ltcfpga.com/ which seems fairly advanced (but NOT opensource)

I'm currently working on an opensource implementation (just for the LOLs), using the on-chip FPGA ram (it needs 1Mbit per hasher core). I've got the simulation running fine using a register array for ram. Unfortunately I'm only estimating around 1khash/sec performance per hasher core. The next step is to port it to my DE0-Nano board (it can only fit half the scratchpad, so its going to interpolate which is even slower). I'll post it on my github once its in a presentable state.

[goxed]

why don't you try developing scrypt mining for LTC for opensource community. There's avery high demand for it IMO.

Jasinlee has a project running at http://ltcfpga.com/ which seems fairly advanced (but NOT opensource)

I'm currently working on an opensource implementation (just for the LOLs), using the on-chip FPGA ram (it needs 1Mbit per hasher core). I've got the simulation running fine using a register array for ram. Unfortunately I'm only estimating around 1khash/sec performance per hasher core. The next step is to port it to my DE0-Nano board (it can only fit half the scratchpad, so its going to interpolate which is even slower). I'll post it on my github once its in a presentable state.

That's awesome kudos to you. Would it be possible to load it on github so others can also try to use  your scrypt miner?

[goxed]

Just a quick update. I did finally get the OpenCL Kernel done and compiling. But I had problems running it, and one of my power supplies went bad. I have two power supplies for my computer, since I have two 5970 cards. I don’t know if the two where related or not. I believe the power supply is under warranty, so I will have to send it in. I do have a spare, plus I can always run one power supply with one card plugged in.

But I am going to skip the OpenCL. I have gotten my second pre-design done, and it has better space savings then the first. I will not report the space savings, since I don’t want people trying to figure out what I am doing. However it is another good space savings jump, but not as good as the last one. Also, I can continue to pipeline the data too. The design is very performance driven. It should be easy to meet timing with this design. I don’t think I am going to get any better than this design, so I am going to start writing the Verilog code starting tomorrow, while my wife and daughter are out. I drew out the first few stages, so I have a guide to follow.

[kramble]

I haven’t looked into scrypts too much, but will work on it after this project. I can re-use the SHA-256 circuit for the scrypts project.

You mentioned you needed 1Mbit of ram per hasher core. What is the gear ration between the hasher and the RAM? Is it 1:1, or some other ratio? Basically, if the hasher runs at 100MHz, what speed is the RAM running at?

Thanks,

Doom

I'm running the core at 25MHz (it didn't seem worth pipelining the salsa mix, given that scrypt is essentially a serial algorithm, so I've implemented it as one huge combinatorial tree), and clocking the on-chip ram at the same speed (just to keep it simple). Using the on-chip ram makes the ram interface very simple as its just a 1024bit wide data path. External RAM (as would be needed for to get any sort of performance from the fpga) is going to be more complicated and would need to run faster, which might make pipelining the salsa worthwhile. Bear in mind that I'm a complete amateur with FPGA/logic design, so don't expect anything sophisticated 

Anyway you can take a look at my code here https://github.com/kramble/FPGA-Litecoin-Miner any suggestions would be welcome. I created a thread to discuss it earlier today in the altcoins section https://bitcointalk.org/index.php?topic=260598.0

[aspeer]

Only if you were here a year ago, now this is a bit late if not obsolete very soon. I'm hoping the best and I'm very interested to see how well you manage to do with this project.

Yeah, looking back on this, I should have skipped the Crypto Extractor/Dominatrix Engine and went straight for the FPGA. But the good thing is there still a huge demand out there. The ASIC companies cannot meet demand, but how long with that be? But that is playing the “what if” game, and I have learnt to never play that game.

But on the flip side, there is a ton of FPGA miners out there. If I can give them a large boost in performance, it might make them last a little longer. Also there is scrypt (Litecoin) after this. Since scrypt uses a SHA-256 circuit, I can re-use it. I believe there still time for Litecoins.

But there is one more big plus. I might be able to work with an ASIC company. They would love to have a design that can drastically increase performance, which can give them an edge over their competitors. And if I can get it working on a FPGA, it just proves the design works. Plus, I was an Electrical Engineer with a proven track record with papers and patents, before becoming disabled. So there is still a large benefit out there. But this is majorly putting the cart in-front of the horse. I still got a lot of work to do, and being disable it comes and goes. But it looks very very promising right now, and I have nothing to lose and everything to gain.

your work is appreciated, im going to run mine until it costs more in power than its worth just to contribute to the network.

[dogie]

Guys you do realise he is trying to improve FPGA efficiency, and patent the results? This is a hell of a long way from open source.

[xyzzy099]

Guys you do realise he is trying to improve FPGA efficiency, and patent the results? This is a hell of a long way from open source.

OMG he's been outed as a Capitalist!  Someone kill him before he gets away!   

Improving on stuff and making a profit from his efforts!  This cannot be endured...

 

[papamoi]

hi

on wich fpga you ll use as basis ?

maybe it ll be interesting to make an asic from your fpga vhdl if it gives better hashing power so we ll be able to get a more powerful asic

keep us posted

[kramble]

Cool, thanks for the info. I definitely will have to learn more about scrypts. I downloaded the paper, but just skimmed the info. One day, I will have to sit down, and go through how it hashes the data.

Yeah, I would definitely pipeline the data. Having a long combinational path will make it really slow. This is where the fun stuff happens. You have to figure out how many stages are the best. Then adding in memory makes it more of a challenge. I wonder if you can run the ram 2x as fast and have 0.5Mbits instead of 1Mbits. This will save some space, plus you will learn how to deal with different clock gearing. But I don’t know if that is possible or not, and you need the 1Mbits.   

No worries on the code. I am glad to see it is written in Verilog (more personal preference than anything). We all have to start somewhere.

My live code for my DE0-Nano board is actually using a 0.5MBit scratchpad (the EP4CE22 chip only has 600kBit ram), so I have to interpolate the missing half of the scratchpad (basically one extra pass through the salsa-mix for half the addresses). I can't really see how I can parallelise this as each ram read address depends on the results of the prior salsa-mix (scrypt was explicitly designed to be awkward to parallelise). From some reading I've seen that a larger scratchpad eg 8MBit can speed up the scrypt, which I don't quite understand yet, so once I've read up some more on it then perhaps some tricks will be apparent (yeah, I just wanted to get something running quickly so I coded a direct analog of the cgminer CPU scrypt.c code, rather than doing my research first  )

The pipelining of the salsa-mix is definitely an issue, but its tricky due to the dependency of the scratchpad reads on addresses generated from the prior salsa. Adding extra register stages allows a faster clock, but needs extra clock cycles to complete, completely cancelling out any gain (and there is no gain from the pipelining itself due to the address dependancy). Once I understand the algorithm better, perhaps I can come up with a solution (I'll need to take a look at the CUDA code to see what's done on the GPUs).

Thanks for the kind words, and good luck.

[goxed]

Guys you do realise he is trying to improve FPGA efficiency, and patent the results? This is a hell of a long way from open source.

OMG he's been outed as a Capitalist!  Someone kill him before he gets away!   

Improving on stuff and making a profit from his efforts!  This cannot be endured...

 

At the time, Intel just launched their Itanium CPUs. So a month later, I got 2 brand new Itanium machines, and one with 128gigs of RAM and another with 64gigs. This had to be 12 years ago. At the time, I had more RAM, than most people’s hard drives. It was awesome.   

Itaniums had $hitty performance for all our X86 code, even recompiled with icc. Personal experience on SGI ALtix Itanium2 based servers. I think it was an EPIC sic. fail

[Milan77]

@DoctorDoom

Please consider implementing SHA1 salted algorhytm also, for bruteforce SL3 logs.
And I hope that You WILL MAKE MONEY with this. I wish you to be like that.

There is nothing wrong to make money with inventions. Nikola Tesla had a lot of great ideas, but he did not make any money on them. So what happened is that he had to beg for money to keep projects running and most of them are never finished. And biggest looser was a mankind.

[dogie]

This community rewards good deeds with donations, not forced patent license fees. Do you really think anyone will pay you when you require a fee? No thanks, first person to get the tweaks will leak all over the internet. Have fun trying to collect a dime.

[Ridicuss]

Doom,

Thanks for the work you put into this. I think it is great that the FPGa guys may be able to extend the life of their rigs, I for one would pay if its a reasonable cost to have an upgrade done. Thanks for your efforts and I hope it takes off.

Damn I must believe in capitalism I am willing to pay for something. GASP!!

[dogie]

Also, I am not forcing anybody to do anything. They have a choice if they want my services or not. If they think I am charging too much, they can pass.

Yes you are. By patenting a new process, you're removing that process from the world for 20 years. No one can use it, release it or do anything else with it without giving you money.

[fpgaminer]

DoctorDoom, I'm going to be straight with you.  Beyond learning/fun, there is absolutely zero reason to invest your time in optimizing a design for the Spartan 6 LX150 platforms.  As I said before, BitFury's open source design for the Spartan 6 LX150 is already at the zenith and will not be surpassed by any meaningful margin.  That design achieves ~300MH/s and should work on all existing Spartan 6 LX150 based miners (X6500, Icarus, Lancelot, Quad, etc).

I say this, because, from what I gather from your posts, you sound like an intelligent, creative, and hard working fellow.  I do not want to see those talents burned on a fruitless task.  If you're only doing this for fun/learning, then by all means continue.  But it sounds like you seek to benefit others from your work, and to profit from your work.  To achieve either or both of those goals I encourage you to focus your efforts elsewhere.

BitFury's design needs porting to the existing FPGA mining platforms.  It's really minimal work, and would boost everyone's performance by 50%.  That would benefit people very immediately, and I'm sure people would pay you for it.

Or you could focus on a strictly ASIC design, an scrypt miner, SL3 cracker, etc.  There are plenty of fruitful opportunities around.

Sorry if this post sounds malicious.  That is not my intention.  I'm not normally this blunt, but I've seen one too many threads like this.

[Syke]

Good luck beating the other bitstreams. A lot of work has already gone into optimizing mining. And since FPGAs generate so little bitcoins now, and every day you delay finishing your bitstream that number dwindles even further, there's just not going to be any interest in paying more than a few pennies for a new bitstream.

[LainZ]

Hello DoctorDoom,

You seem late to this game !

hopefully I am pretty confident that your skills will interest one of those ASIC firms out there...(if you are what you pretend to be)

Your life is a tragedy. If it works out though, seeing your past work history...and throwing

3x

performance!

If not for you being disabled, if not for bitcoin very existence, then you could not support your family with just a little fun and spare time.Maybe even becoming "wealthy'.<- this headline is incredibly hard to believe, seems so fuckin good to be true.

Best of luck!

LainZ.

Also already job offers:

We are hiring! If you are skilled in IC design / HDL optimization, shoot us your CV at info@labcoin.com

Try contacting friedcat, ngzhang, bitfury, aiwill also.

[turtle83]

Even having a hundred dollars or two a month would be nice

How about this. Send bitstreams to early adopters with understanding that they do not share the bitstream with anyone (unless you ever decide to make it public), and they send you the earnings from the delta for 2 weeks.

Example I have 11 Ztex 1.15y (44 LX150 chips total) currently at ~9.5 GH/s. If you make it 3x = 28.5 GH/s , i would gladly pay you 19 GH/s worth of mining proceeds for 2 weeks. I would in fact point the equivalent number of boards to a pool of your choosing. Thats $30.84/day from me alone at todays difficulty, maybe by the time ur done its $10/day... maybe lesser...

I am sure im not alone in accepting this kind of offer... but this requires a leap of faith on both sides. (You trust that i donate the promissed hashrate to you, and I trust that you dont have something evil like timebombs in the bitstream)...

^ If you decide to opensource it(and provide bitstream that works with ztex firmware) , id donate a months worth of extra hash rate.

[klee]

Dude ever considered ALCOR or Cryogenic Institute? That can keep you motivated, second chance. Though even this may won't be necessary - Singularity/Immortality is near! See 2045.ru ...
But you will need money! Finish this shit and I hope we can gain something too in a win-win scenario. We already do.
Cheers!