Monarch butterfly prototype

[xstr8guy]

Either I'm a bit thick or Josh is an excellent strategist, but surely you have to buy a motherboard, a case and a PSU for every pair of these PCI cards? At 350W per card I can't see more than two being powered by a 850W PSU, maybe three at a stretch with a super expensive 1200W PSU. Is the community clamouring for this form factor?

Given BFL's history on predicting heat output on their previous product range I can see many issues on getting your case adequately ventilated as well. Perhaps Josh's new strategy is to delegate all real world problem solving to the customer now. Win!

Supposedly they don't need to be attached to a motherboard.  They can be freestanding and controlled by USB. At least that's what they said at launch.

[1714904626]

1714904626

[1714904626]

1714904626

[1714904626]

1714904626

[greyhawk]

Christ that thing is huge. Finally we're going to get more haphazardly kludged together fire hazards.

[joeventura]

I have to admit, this is encouraging to me.  I have an early preorder so I have to hope for the best.

[joeventura]

Christ that thing is huge. Finally we're going to get more haphazardly kludged together fire hazards.

Don't you see the ETL/FCC and CE logos on the card??

It's safe!!!

 

[donch]

BFL, the fail that just keeps on giving.

[Nemesis]

I'm surprised BFL still use Nasser and not working with a real engineering firm. I dont know what the deal between them, Nasser is probably a co-owner to make any sense.

I despite Nasser because he sucks and fcked up every single design.

Look at all the new 28nm ASIC companies, they can finish within MONTHs because they have a proper engineers working for them. I'm sure this has caused BFL alot more than saving by hiring ONE lame engineer working abroad.

[YipYip]

I'm surprised BFL still use Nasser and not working with a real engineering firm. I dont know what the deal between them, Nasser is probably a co-owner to make any sense.

I despite Nasser because he sucks and fcked up every single design.

Look at all the new 28nm ASIC companies, they can finish within MONTHs because they have a proper engineers working for them. I'm sure this has caused BFL alot more than saving by hiring ONE lame engineer working abroad.

He is gurateed in on the action.....

[dogie]

I'd like to see his accreditation, to see if we can strip him of it.

[MrTeal]

Christ that thing is huge. Finally we're going to get more haphazardly kludged together fire hazards.

Don't you see the ETL/FCC and CE logos on the card??

It's safe!!!

 

Well, there aren't actually any traces yet, so I'd imagine it will be quite safe. It might just be an early component layout so that they can get the physical dimensions nailed down.

[Wardan_reloadeD]

Danaus plexippus

http://es.wikipedia.org/wiki/Danaus_plexippus

Dont trust BFL anymore, they fails 8 months of theirs prediction.

The difference in ROI is from 150 to 15 BTC.

THANKS BFL, i loose the ASIC train.

http://upload.wikimedia.org/wikipedia/commons/thumb/6/63/Monarch_In_May.jpg/330px-Monarch_In_May.jpg

[Loredo]

Pretty big chips, not as big as the KNCminer ones but still large, looks like 1,020 pins.

1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, yes, you're right

 

Step away from your monitor NOW.  Go immediately to the optometrist and have your eyes checked.

[DeathAndTaxes]

How the hell are they going to deal with the cooling needs if these are supposed to be packed next to each other in PCI-E slots?

Simple you will only be able to mount 1 or 2 per computer chassis and thus defeating the major "advantage" of a "datacenter ready card".

[Loredo]

Christ that thing is huge. Finally we're going to get more haphazardly kludged together fire hazards.

Don't you see the ETL/FCC and CE logos on the card??

It's safe!!!

 

Well, there aren't actually any traces yet, so I'd imagine it will be quite safe. It might just be an early component layout so that they can get the physical dimensions nailed down.

Yes, that is my opinion, too.  The date on the board is August, as can be seen by zooming up.

[krayzie32]

Christ that thing is huge. Finally we're going to get more haphazardly kludged together fire hazards.

Don't you see the ETL/FCC and CE logos on the card??

It's safe!!!

 

Well, there aren't actually any traces yet, so I'd imagine it will be quite safe. It might just be an early component layout so that they can get the physical dimensions nailed down.

Yes, that is my opinion, too.  The date on the board is August, as can be seen by zooming up.

Plus the one chip is cocked a little bit in the center of the board so there is no way it was soldered to a trace the way it sits now.  Early board layout for sure, not a prototype by any stretch of the imagination.

[joeventura]

From the BFL Forums:


There are some VERY poor design choices on that board:

While a switch to what appears to be a 5-phase regulator per chip is a very good design choice, the choice to use a non-synchronous regulator (you can spot one of these by the need to use a diode(s) in the power path) is very poor.

1/ Synchronous regulators are more efficient than non-synchronous regulators, particularly at low voltages.
2/ Non-synchronous regulators require a diode powerful enough to handle the full current of the output. (That's a BIG diode!)
3/ BFL engineers appear to think they can use lots of smaller diodes in parallel instead of one big diode - that's a big no-no! Google 'diodes in parallel' if you care to know why!

I can't remember the last time I saw a motherboard which had anything other than a multi-phase synchronous regulator for the CPU - and they don't have to deliver as much power as the Monarch does!

[DeathAndTaxes]

For those that are interested I eyeball the package size at ~34mm x 34mm.  How?  The power connector is a standard part with 13.8mm width (for 6 conductors).  http://www.molex.com/elqNow/elqRedir.htm?ref=http://www.molex.com/pdm_docs/sd/050362377_sd.pdf  In the photo using that component as a reference we can calculate the resolution at 5.36 pixels per mm.  That puts the package size at ~34mm by 34mm.


However it makes me wonder even more how they intend to dissipate that level of energy density.  If we assume BFL power requirements are accurate and the DC to DC regulators are 90% efficient.  Then 350W *0.9 / 2 = 157.5W per chip.  At 11.56 cm2 that is 13.6 W/cm2.  This is already high and BFL doesn't have a very good track record of accurate power simulations.  At 20% over it would be ~14 W/cm2 and at 50% over it would be ~17 W/cm2.  These are some pretty challenging Heat fluxes.

How does the heat flux compare to other ASIC products.  KNC package is 20.25 cm2 and chip only power consumption is ~160W.  That is 7.9 W/cm2.  Now take a look at how large the heat sink and fan is for a single chip and double it.  HashFast package size is also 20.25 cm2 and chip only power consumption is ~250W.  That works out to 12.34 W/cm2.  HashFast is using waterblock (water has 20x the thermal conductivity of air) to remove that level of energy density.

[Loredo]

From the BFL Forums:


There are some VERY poor design choices on that board:

While a switch to what appears to be a 5-phase regulator per chip is a very good design choice, the choice to use a non-synchronous regulator (you can spot one of these by the need to use a diode(s) in the power path) is very poor.

1/ Synchronous regulators are more efficient than non-synchronous regulators, particularly at low voltages.
2/ Non-synchronous regulators require a diode powerful enough to handle the full current of the output. (That's a BIG diode!)
3/ BFL engineers appear to think they can use lots of smaller diodes in parallel instead of one big diode - that's a big no-no! Google 'diodes in parallel' if you care to know why!

I can't remember the last time I saw a motherboard which had anything other than a multi-phase synchronous regulator for the CPU - and they don't have to deliver as much power as the Monarch does!

Just another example of how they work, marketing/sales, and not technology, driven as they are.

For every one person who can spot an off-angle placement, or has the knowledge to assess the board's technical efficacy, there are hundreds of others who cry "Oh boy, oh boy!  Just two more missing pieces and my Money Machine is ready to go!"

They are the same ones who cry, when McDonald's is having their Monopoly game, and they get a "Park Place" game piece and cry "Oh boy, oh boy!  Just one game piece to go to get my million dollars."  But their money is good, and they buy lots of Big Macs to try to get it.

[DeathAndTaxes]

I can't remember the last time I saw a motherboard which had anything other than a multi-phase synchronous regulator for the CPU - and they don't have to deliver as much power as the Monarch does!

What about GPU?  Honest question I have no idea.

Here is a HD 7970 PCB.
http://www.techage.fr/picto/photosredac/pcu57/radeon/HD7970-PCB.jpg
http://www.techage.fr/picto/photosredac/pcu57/radeon/HD7970-Alim.jpg

[rograz]

If we assume BFL power requirements are accurate and the DC to DC regulators are 90% efficient.  Then 350W *0.9 / 2 = 157.5W per chip.  At 11.56 cm2 that is 13.6 W/cm2.

It's not unheard of with higher power density/mm2 for 2 slot coolers, Nvidia GTX 480 was a inefficient leaky monster and those things only caught fire sometimes!

[Puppet]

To put that into perspective KNC package is 20.25 cm2 and chip only power consumption is ~160W.  That is 7.9 W/cm2.  Take a look at how large the heat sink is for KNC boards.   HashFast package size is also 20.25 cm2 and chip only power consumption is ~250W.  That works out to 12.34 W/cm2.  HashFast is using waterblock (water has 20x the thermal conductivity of air) to remove that level of heat.

Thats not entirely fair. You measure the size of a heatspreader, the actual diesize will determine the thermal density and for KnC's sake, I hope thats no where near 1000mm². Moreover, the entire surface of these asics will generate about the same amount of heat per mm² very uniformly . On a modern cpu,  something like 90% of the power is used by the cpu core which in most cases occupies only a small fraction of the die (the rest is cache, memory controller, etc). Im too lazy too look up numbers, but Im pretty sure a highend cpu will have a far higher thermal density at its core than any of these asics.  Silicon has fairly good thermal conductivity, mitigating the problem for cpu's to some extend, but its no were as good as copper or even aluminum.

So thermal density isnt going to be problem with these chips. Of course you still need to get rid of 100's of watts of power, no doubt that requires a serious cooler, but the size of the chips wont make a lot of difference.