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Author Topic: [ANN][BLC] Blakecoin Blake-256 for GPU/FPGA With Merged Mined Pools Stable Net  (Read 402998 times)
gymnastico
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January 06, 2014, 05:43:13 PM
 #1121

Pool is still offline now, the address is correct, try in solo  Smiley
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January 06, 2014, 05:52:15 PM
 #1122

yay the pool just sent me the blc which had been uncomfirmed in my account at the time the pool went down. must mean something is happening behind the scenes, hopefully pool will be back up soon?
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January 06, 2014, 06:07:04 PM
 #1123

Pool is back up. Sadly I don't have the time I had at the beginning of the project to maintain the pool, so I'm open to offers to sell it, it will include everything, domain name, server, etc. If nobody is interested, I will keep maintaining it on my spare time.




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January 06, 2014, 06:12:19 PM
 #1124

Pool is back up. Sadly I don't have the time I had at the beginning of the project to maintain the pool, so I'm open to offers to sell it, it will include everything, domain name, server, etc. If nobody is interested, I will keep maintaining it on my spare time.
Can you explain to me what was happened with my account with coins "Unable to login: Account is locked. Please contact site support."
my nick is on you  PM
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January 07, 2014, 07:50:54 AM
 #1125

good to see a coin with something different
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January 07, 2014, 12:49:44 PM
 #1126

good to see a coin with something different

yes! it resembles the start of BTC (few people mining , 1 pool with problems, wallet problem... etc)
i hope to have the same progress :p
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January 07, 2014, 03:43:31 PM
 #1127

Do You plan to support Ztex 1.15x fpga boards for mining? I've got four of them lying down around and could play with them.
Is there only need to bitstream changes or in cgminer sources too?

If bitstream then I think that constraints file changes will not be enough to work ztex 1.15x properly because of CPLD chip absence in 1.15x version.

Could You give me any other hints, i'll give a try. Contraints .ucf file changes should be easy for me, I've done some easy HDL projects so far.

BR
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January 07, 2014, 04:09:01 PM
Last edit: January 09, 2014, 05:57:02 PM by kramble
 #1128

Do You plan to support Ztex 1.15x fpga boards for mining? I've got four of them lying down around and could play with them.
Is there only need to bitstream changes or in cgminer sources too?

If bitstream then I think that constraints file changes will not be enough to work ztex 1.15x properly because of CPLD chip absence in 1.15x version.

Could You give me any other hints, i'll give a try. Contraints .ucf file changes should be easy for me, I've done some easy HDL projects so far.

Its been requested but I've been taking a bit of a break from coding recently (a touch of burnout, not helped by the tendency of the Xilinx ISE to arbitrarily refuse to route stuff).

The bitcoin mining verilog source code and Cypress MCU firmware is a good resource (link), specifically the source package (link).

I think the 1.15x is compatible with the 1.15b code, though looking at the web page it has different hash rates (due to different devices LX150 vs LX75), so I'm not so sure now. EDIT, ah its actually the 1.15d that's compatible with the 1.15x, so scratch what I said about the 1.15b, and the following paragraph is now irrelevant.

IGNORE ... I made a start on a port for my litecoin miner to the 1.15b a good while back (link) but never got as far as testing (I don't have one, and it was really just as a discussion point with another member, vpereira, who's rather dropped out recently), but it may be of interest. Not that the litecoin project is going anywhere, the hash rates were just too low to be useful.

The absence of the CPLD just affects the bitstream upload time, the actual firmware runs on the Cypress EZ-USB chip and it claims to be compatible (link). Cgminer should be fine but you'll need to replace the correct bitstream file. Its a bit confusing as there are d1, d2 and d4 versions. I assume the correct one is selected depending on the version of the board? I'd need to dig through both the verilog and the firmware source code to check this. OK, probably just the d4 variant you want to use (the d1 and d3 seem to just be earlier versions of the code with slightly different interfacing which might confuse cgminer). Actually cgminer was the hardest part of getting the ztex 1.15y port working, so may well be an issue here. Its easiest to build on linux if you need to tweak it, but its doable on windows with a bit of hassle to get the build environment set up properly.

I did a diff between the bitcoin d4 and y1 code, and its just the select logic that's different (and a tweak to pll_stop buffering which seems irrelevant). So assuming d4 is good for the 1.15x, then it will just need a small change to the blakecoin top to make it work, plus using the 15.ucf rather than the 15y.ucf. Compiling it, this may take a little while. <rant> GRR, this is going to take hours and it probably won't even meet timing closure which means it'll be slower than if I'd chosen a more lax clock constraint. I hate ISE. So to stop it now and retry slower, or with different tables? Or just let it run and hope it completes sometime today? GRR. </rant> OK, I dropped a core to get a faster build (redacted, see note below). Copy it over bitstreams/ztex_ufm1_15d4.bit. It won't clock very fast so I'd suggest --ztex-clock 150:150 initially. If it works I'll try to get a faster dual core version to build (it'll take several days of tweaking, damn ISE). Otherwise its debug time Sad

Good luck, me know how you get on.

EDIT: I've been told (via PM) that the bitstream linked above is broken so DO NOT USE IT (now redacted, I was using the wrong hashcore, an experimental 4 core version instead of the standard 1.15y hashcore), but hal7 does have a working version which I have hosted on dropbox (bitstream link) Use --ztex-clock 128:128 for 250MHash/sec. It will probably clock a little faster (YMMV).

EDIT (9 Jan) Faster version (again courtesy hal7)
https://www.dropbox.com/s/4nnquv6z66an6c5/hal7_ztex_ufm1_15d4_2core_v02.bit
Results (min. 1h tests):
Ztex 1.15x clone - grade 2 chip: 144MHz stable with 0 HW, 6.2W power with 40mm fan
Ztex 1.15x         - grade 3 chip: 152MHz stable with 0 HW, 7.0W power with 40mm fan (>300MH/s)

Github https://github.com/kramble BLC BkRaMaRkw3NeyzsZ2zUgXsNLogVVkQ1iPV
hal7
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January 07, 2014, 10:28:09 PM
Last edit: January 07, 2014, 11:02:00 PM by hal7
 #1129

Thanks for hints. Indeed select logic is different, and three or four other lines need small changes.

I've succesfully compiled cgminer 3.1.1 with your patched sources under Debian 6, good work!:) ; it can detect and work with 1.15x board, but of course it is doing HW only because of original ztex bitstream... but it sends work:). I've started doing changes to original 1.15d4 verilog code. Wasn't so hard and even synthezises. But how did you constrained TIMESPEC clk PERIOD? From where did you get 100MHz 50%? NET fxclk_in is driven by 48MHz from Cypress FX2.

Now waiting to implement design.. hours or days with Smartxplorer...
tuned: resource sharing off, register duplication on, equvalent register removal off, register balancing yes
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January 07, 2014, 10:29:58 PM
 #1130

one question, is it possible to send some amount of blc to multiple addresses at once?

There should be a api method sendmany. You can check the bitcoin api documentation for the format. Its also listed when typing "help" into the debug console. I am assuming it works.
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January 08, 2014, 02:25:58 AM
 #1131

I have another pool working but needs some tweaks to the mpos front end as all the dashboard graphs and hash rates are not displayed correctly but shares and payouts are working Cheesy

I have also done/tweaked some install/run scripts for ubuntu 12.04 which helps running a private/public pool Cool

hope to have some releases for this weekend, if I am not about as much over next few days its just me finishing this work off  Wink

Info: GithubBlakecoin.org - BCT Blakecoin thread - Twitter - BCS - BlakeZone  Trade Blakecoin: Cryptopia - C-patex Merged Mining Pools: EU3 - NY2/AT1 - LA1
Donation Addresses: BLC: Bd3jJftFbwxWSKNSNz35vkDd57kG6jHAjt PHO: BZXPMc8eF9YZcJStskkP2bVia38fv9VmuT BBTC: 2h8c4NbzXJXk6QQ89r7YYMGhe13gQUC2ajD ELT: e7cm6cAgpfhvk3Myh2Jkmi1nqaHtDHnxXb 
UMO: uQH9H17t7kz3eVQ3vKDzMsWCK4hn5nh2gC LIT: 8p8Z4h5fkZ8SCoyEtihKcjzZLA7gFjTdmL BTC: 1Q6kgcNqhKh8u67m6Gj73T2LMgGseETwR6
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January 08, 2014, 10:31:08 AM
 #1132

But how did you constrained TIMESPEC clk PERIOD? From where did you get 100MHz 50%? NET fxclk_in is driven by 48MHz from Cypress FX2.

The constraints could do with a bit of expert attention. I changed it from Stefan's original code at around the time I dropped the second PLL. It just made more sense to me to constrain the DCM output rather then the osc input, that way its easier to tweak the clock value to optimize the FMAX (the DCM multiplier is dynamically configured at runtime). The general procedure I use is to gradually increase TS_clk while tweaking the PAR -t parameter for multiple builds until I get fed up with the entire procedure. I suppose SmartExplorer would be the professional approach to this, but it seems to be designed for use with a farm of build machines (the one time I tried it, it fired off four parallel builds and thrashed my poor little machine).

I've posted some code up on the github (link). The bitstream I created upthread used a modified version (delete core M2, remove the phase switch logic) but these are fairly trivial changes (I ought to configure it with `ifdef but this was just a quick'n'dirty hack to get something built in a sensible timeframe).

Best of luck with ISE, you'll need it  Angry

Github https://github.com/kramble BLC BkRaMaRkw3NeyzsZ2zUgXsNLogVVkQ1iPV
knorrly
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January 08, 2014, 11:03:34 AM
 #1133

But how did you constrained TIMESPEC clk PERIOD? From where did you get 100MHz 50%? NET fxclk_in is driven by 48MHz from Cypress FX2.

The constraints could do with a bit of expert attention. I changed it from Stefan's original code at around the time I dropped the second PLL. It just made more sense to me to constrain the DCM output rather then the osc input, that way its easier to tweak the clock value to optimize the FMAX (the DCM multiplier is dynamically configured at runtime). The general procedure I use is to gradually increase TS_clk while tweaking the PAR -t parameter for multiple builds until I get fed up with the entire procedure. I suppose SmartExplorer would be the professional approach to this, but it seems to be designed for use with a farm of build machines (the one time I tried it, it fired off four parallel builds and thrashed my poor little machine).


You can configure the number of parallel runs in SmartXplorer in the "Launch SmartXplorer" dialog:

- On Windows: set the "Number of parallel runs on this machine"
- On Linux: for each run, add a host to host list file

See http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ise_c_using_smartxplorer.htm, "To Run SmartXplorer from Project Navigator", items 3 and 4.
gielbier
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January 08, 2014, 11:18:47 AM
 #1134

BLC on exchange.

https://openex.pw/index.php?page=trade&market=6


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January 08, 2014, 11:35:49 AM
Last edit: January 08, 2014, 12:19:12 PM by kramble
 #1135

You can configure the number of parallel runs in SmartXplorer in the "Launch SmartXplorer" dialog:

- On Windows: set the "Number of parallel runs on this machine"
- On Linux: for each run, add a host to host list file

See http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ise_c_using_smartxplorer.htm, "To Run SmartXplorer from Project Navigator", items 3 and 4.

Thanks. I'm just an amateur hacker on ISE, so any advice from the pro's is most welcome Cheesy

Hal7's 1.15x bitstream is now hosted on dropbox (link to README)

Github https://github.com/kramble BLC BkRaMaRkw3NeyzsZ2zUgXsNLogVVkQ1iPV
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January 08, 2014, 01:41:59 PM
 #1136

You can configure the number of parallel runs in SmartXplorer in the "Launch SmartXplorer" dialog:

- On Windows: set the "Number of parallel runs on this machine"
- On Linux: for each run, add a host to host list file

See http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ise_c_using_smartxplorer.htm, "To Run SmartXplorer from Project Navigator", items 3 and 4.

Thanks. I'm just an amateur hacker on ISE, so any advice from the pro's is most welcome Cheesy


I think you are doing a terrific job!

I forgot to mention that in order to run N builds in parallel on the same machine you have to add this machine N times to the host file (on Linux). You can use "localhost".
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January 08, 2014, 04:19:39 PM
 #1137

I think you are doing a terrific job!

Not quite such a good job. I've now worked out why my initial 1.15x bitstream was broken. I was using an experimental 4 core pipeline instead of the 2 core pipeline (the offsets are different since the nonce is distributed by LSB rather than MSB). My fault, its been a while since I worked on the verilog and I just copied what I thought was current rather than taking the actual code used from the github, so I used work-in-progress rather than verified code. I've updated the github now, the 1.15x and 1.15y pipelines should now be identical.

Github https://github.com/kramble BLC BkRaMaRkw3NeyzsZ2zUgXsNLogVVkQ1iPV
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January 08, 2014, 05:24:48 PM
 #1138


looks like no one really uses that exchange yet, but any exchange is better than none to start with. From their twitter it seems the site only went live within the past few days. However I've listed some blc for sale there just in case. It looks like a good site though, I'm glad it's open source. If we all start using it to trade blakecoin, perhaps we can give openex some credibility.
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January 08, 2014, 11:52:57 PM
 #1139

I'm having a problem, my wallet won't update automatically. So I have to restart my computer or close & reopen the wallet to update the wallet.
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January 09, 2014, 04:44:58 PM
 #1140

I'm having a problem, my wallet won't update automatically. So I have to restart my computer or close & reopen the wallet to update the wallet.

Are you solo Mining? This seems to happen if your PC is not on UTC time and you solo mine.

You can join a pool or set timezone on you PC to UTC/0GMT or set a timer to turn Wallet off then back on every 2 hrs or so.

Merge mine BLC+PHO+ELT+XDQ+BBTC+UMO+LIT pool is open http://la1.blakecoin.com tips: 1MogRiTHpQZ7bkpq49cSVWADrTt7Jrghp
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