The claimed hashrate isn't supported by the available bandwidth of the memory they're using. Their design shows they are using dual DDR4 SO-DIMMs, so if we assume they are using the fastest SO-DIMMs available (eg. GSkill displayed their fastest kits at Computex 2018: DDR4-4200 SO-DIMMs,
http://www.gskill.com/en/press/view/g-skill-showcases-extreme-ddr4-memory-kits-up-to-ddr4-5066mhz-at-computex-2018 ), then this "router-miner" design would have a 128-bit wide memory bus (ie. dual 64-bit bus SO-DIMMs) at 4.2 GHz data pin speeds. This would give them an effective bandwidth of around 67.2 GB/s.
Since a single ETH hash samples 8192 bytes from the DAG (ie. 64-iteration loop of 128 bytes per iteration), then the 67.2 GB/s bandwidth would give a theoretical, zero-latency hashrate of around ~8.2 MH/s. Pretty far off from the claimed 21 MH/s.
The alternative approach of storing just the much smaller light-DAG in the FPGA block RAM and generating the full DAG entries during the ETH sampling loop by brute-force/"on-the-fly" would require around ~11 INT32 TOP/s processing capability (ie. 256K FNV operations or equivalently 512K INT32 operations per ETH hash) for the claimed 21 MH/s hashrate. The FPGA series they are using (Zynq Ultrascale+,
https://www.xilinx.com/support/documentation/selection-guides/zynq-ultrascale-plus-product-selection-guide.pdf ) has at most around 1.1M logic cells and 1.9K DSP slices. By comparison, the much larger Virtex Ultrascale+ VU9P (as used on the VCU1525 and the mining BCU1525 card) has 2.5M logic cells and 6.8K DSP slices and is rated at around ~5.3 INT32 TOP/s (
https://www.xilinx.com/support/documentation/selection-guides/ultrascale-plus-fpga-product-selection-guide.pdf ). Still under the ~11 INT32 TOP/s needed to brute-force DAG entry generation "on-the-fly".
So whether via DAG sampling from the DDR4-SODIMM, or alternatively via brute-force DAG entry generation, it would seem that this "miner-router" doesn't have the specs to do 21 MH/s for ETH.
