Bitcoin Forum
September 18, 2019, 12:24:22 PM *
News: Latest Bitcoin Core release: 0.18.1 [Torrent]
 
   Home   Help Search Login Register More  
Pages: « 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 [21] 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 ... 100 »
  Print  
Author Topic: DIY FPGA Mining rig for any algorithm with fast ROI  (Read 94635 times)
gameboy366
Jr. Member
*
Offline Offline

Activity: 252
Merit: 8


View Profile
May 06, 2018, 06:00:24 PM
 #401

Yo ! Can Workstation gpus outperform gaming gpus in mining. One guy here said that they are like fpga (or I didn't understand correctly). Can they be modified and made into a better mining machine ?
1568809462
Hero Member
*
Offline Offline

Posts: 1568809462

View Profile Personal Message (Offline)

Ignore
1568809462
Reply with quote  #2

1568809462
Report to moderator
Transactions must be included in a block to be properly completed. When you send a transaction, it is broadcast to miners. Miners can then optionally include it in their next blocks. Miners will be more inclined to include your transaction if it has a higher transaction fee.
Advertised sites are not endorsed by the Bitcoin Forum. They may be unsafe, untrustworthy, or illegal in your jurisdiction. Advertise here.
HardwareCollector
Jr. Member
*
Offline Offline

Activity: 96
Merit: 3


View Profile
May 06, 2018, 06:03:10 PM
 #402


It would be nice to have a complete database documenting all PoW algos (including pseudo-code). If someone feels motivated to do it, I'd be glad to sponsor them.

Can you please elaborate on the sponsorship. I understand the equihash algorithm very well, by the way.
HardwareCollector
Jr. Member
*
Offline Offline

Activity: 96
Merit: 3


View Profile
May 06, 2018, 06:11:12 PM
 #403

Yo ! Can Workstation gpus outperform gaming gpus in mining. One guy here said that they are like fpga (or I didn't understand correctly). Can they be modified and made into a better mining machine ?

No, a Quadro P6000 ($4,999) does not out perform a GTX 1080 Ti ($699) for mining, they are basically the same cards compute-wise.
gameboy366
Jr. Member
*
Offline Offline

Activity: 252
Merit: 8


View Profile
May 06, 2018, 08:16:59 PM
 #404

Yo ! Can Workstation gpus outperform gaming gpus in mining. One guy here said that they are like fpga (or I didn't understand correctly). Can they be modified and made into a better mining machine ?

No, a Quadro P6000 ($4,999) does not out perform a GTX 1080 Ti ($699) for mining, they are basically the same cards compute-wise.
But, but this guy said something like this :
Can workstation cards become useful for mining ? Damn ! They're gonna teach us FPGA next year in college.

You mean the FirePro type GPUs? Definitely. I have many many older FirePro cards that had plenty of memory bandwidth but underpowered (or over powered depending how you look at it) cores compared to the current gen. This cards got large page table support and some other niceties because of who the customers were. The also support an FPGA on the PCIe bus directly writing into / readying from their GPU memory (albeit at PCIe speeds). This works great with something like ETH, because you can do all the compute heavy Keccak off GPU but still use all the memory bandwidth.
Xeonus
Newbie
*
Offline Offline

Activity: 51
Merit: 0


View Profile
May 06, 2018, 09:05:03 PM
 #405

This thread is super interesting to read. As others have stated, it is interesting to see these ASIC, FPGA, GPU cycles and discussions happen over the years.

Are now modern FPGAs (and the ones the OP uses) more suitable than the ones that were used in the previous attempts? Are FPGAs now in a sense more flexible in terms of mining so it makes sense to focus development on those?
Reggie0
Member
**
Offline Offline

Activity: 107
Merit: 13


View Profile
May 06, 2018, 09:22:52 PM
Merited by suchmoon (2)
 #406

From my practice there are simple measures to avoid failures.
Do not place these boards in the closed case, setup the fan to cool the bottom layer of PCB.
Do not allow the local overheat of any component like DC/DC or external power connector.
Turn on the overtemperature shutdown in the bitstream, and control the temperature in the mining software. It is easy.
Then the FPGA board will work for years.

“Turn on overtemp shutdown in the bitstream”

AFAIK there’s no such magic button. If you want temp monitoring and thermal limits with an FPGA you have to include them in your design logic. Same as an ASIC. Otherwise you very much can exceed junction temps and damage the hardware if you have enough power going into the board to begin with.

This is also possible on some GPUs with poor drivers. A few of my old Titan Blacks from HPC work had power stages for memory that would overheat if the memory was trashed too much for too long, and the mosfet would slip down on the boards till they caused a short. Actually caught a entire server on fire that way once...

False. The better fpgas(like virtex 5/6, complete series 7 and newer xilinx) has pin terminals to an separated internal die temperature sensor transistor. A properly designed board should use it for temperature measurement and shutdown. It works even when FPGA isn't configured. An alternative is using jtag to read XADC (7 series and newer).
whitefire990
Copper Member
Member
**
Offline Offline

Activity: 165
Merit: 84


View Profile
May 06, 2018, 09:33:24 PM
 #407

Both the VCU1525 and XUPP3R have a circuit that will shut down the FPGA power supply if the temperature exceeds limits.  This doesn't prevent you from trying to pull too much current for a short time though.

Another important note for people considering this hardware.  The VCU1525 has a fixed core voltage of 0.85V.  The XUPP3R from Bittware is more flexible and you can change the core voltage from 0.74V to 1.11V, which allows a much greater flexibility in terms of over-clocking the FPGA.  For memory intensive algorithms, a higher voltage will produce faster hash rates, vs. for power limited algorithms, a lower voltage would likely produce better hash rates.

2112
Legendary
*
Offline Offline

Activity: 2114
Merit: 1032



View Profile
May 06, 2018, 09:57:59 PM
Merited by suchmoon (2)
 #408

Turn on the overtemperature shutdown in the bitstream, and control the temperature in the mining software. It is easy.
“Turn on overtemp shutdown in the bitstream”

AFAIK there’s no such magic button. If you want temp monitoring and thermal limits with an FPGA you have to include them in your design logic.
False. The better fpgas(like virtex 5/6, complete series 7 and newer xilinx) has pin terminals to an separated internal die temperature sensor transistor. A properly designed board should use it for temperature measurement and shutdown. It works even when FPGA isn't configured. An alternative is using jtag to read XADC (7 series and newer).
I actually went ahead and RTFM'd the "UltraScale Architecture SYStem MONitor User's Guide". It looks like it is very close to being a "magic button", it takes only one line of code:
Code:
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE
On the other hand the whole guide to the SYSMON block has 113 pages, so it must be also relatively easy to accidentally mis-configure it.
 

Please comment, critique, criticize or ridicule BIP 2112: https://bitcointalk.org/index.php?topic=54382.0
Long-term mining prognosis: https://bitcointalk.org/index.php?topic=91101.0
GPUHoarder
Member
**
Offline Offline

Activity: 154
Merit: 37


View Profile
May 06, 2018, 10:22:00 PM
 #409

Turn on the overtemperature shutdown in the bitstream, and control the temperature in the mining software. It is easy.
“Turn on overtemp shutdown in the bitstream”

AFAIK there’s no such magic button. If you want temp monitoring and thermal limits with an FPGA you have to include them in your design logic.
False. The better fpgas(like virtex 5/6, complete series 7 and newer xilinx) has pin terminals to an separated internal die temperature sensor transistor. A properly designed board should use it for temperature measurement and shutdown. It works even when FPGA isn't configured. An alternative is using jtag to read XADC (7 series and newer).
I actually went ahead and RTFM'd the "UltraScale Architecture SYStem MONitor User's Guide". It looks like it is very close to being a "magic button", it takes only one line of code:
Code:
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE
On the other hand the whole guide to the SYSMON block has 113 pages, so it must be also relatively easy to accidentally mis-configure it.
 

I stand corrected, I was not aware of the existence of that flag! I knew you could read the XADC, but did not realize there was a bitstream flag. Good to know, although I don’t know if I would rely on that as your only protection.

I appreciate the wealth of knowledge and skill coming out on this forum regarding the FPGA work.

Regarding workstation GPUs, I said they could be useful for mining, and can work alongside FPGAs given the direct access to their memory, not that they were better than normal GPUs for mining or that they were like FPGAs. You can however very often find large batches of the older generation passive cards for cheap as most people don’t have the ability to use them. I last paid $130/ea about a month ago for a bunch of older FirePro workstation cards that are now hashing at 24MH ea.

senseless
Hero Member
*****
Offline Offline

Activity: 1118
Merit: 541



View Profile
May 06, 2018, 11:18:03 PM
 #410

Both the VCU1525 and XUPP3R have a circuit that will shut down the FPGA power supply if the temperature exceeds limits.  This doesn't prevent you from trying to pull too much current for a short time though.

Another important note for people considering this hardware.  The VCU1525 has a fixed core voltage of 0.85V.  The XUPP3R from Bittware is more flexible and you can change the core voltage from 0.74V to 1.11V, which allows a much greater flexibility in terms of over-clocking the FPGA.  For memory intensive algorithms, a higher voltage will produce faster hash rates, vs. for power limited algorithms, a lower voltage would likely produce better hash rates.

The VCU1525 is also only 160A vccint... Increasing the voltage lowers amperage and allows you to use more power... But, I'm not sure the amperage of supply capacity the bittware board has... Happen to have a product manual on you? If the board is only designed for 100A, wouldn't do you much good even operating at 1V. I've got a couple VCU118's here that I picked up long before the VCU1525 was announced or released. Those are limited to like 80A vccint  Cry and they're damn near twice the price.




Reggie0
Member
**
Offline Offline

Activity: 107
Merit: 13


View Profile
May 07, 2018, 12:05:32 AM
Merited by 2112 (1)
 #411

Turn on the overtemperature shutdown in the bitstream, and control the temperature in the mining software. It is easy.
“Turn on overtemp shutdown in the bitstream”

AFAIK there’s no such magic button. If you want temp monitoring and thermal limits with an FPGA you have to include them in your design logic.
False. The better fpgas(like virtex 5/6, complete series 7 and newer xilinx) has pin terminals to an separated internal die temperature sensor transistor. A properly designed board should use it for temperature measurement and shutdown. It works even when FPGA isn't configured. An alternative is using jtag to read XADC (7 series and newer).
I actually went ahead and RTFM'd the "UltraScale Architecture SYStem MONitor User's Guide". It looks like it is very close to being a "magic button", it takes only one line of code:
Code:
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE
On the other hand the whole guide to the SYSMON block has 113 pages, so it must be also relatively easy to accidentally mis-configure it.
 

You are going too far to look up some useful information, but it is on the top. Read the "VCU1525 Acceleration Platform User Guide", on page 47. It says fan controller IC has a die temperature sensor connected to FPGA-s DXP/DXN pin, and has an TCRIT#output which connected to the supervisory IC and it will shut down the FPGA, when overheated. It is independent from the FPGA and FPGA's SYSMON.

It looks like the Xilinx's card is a properly designed FPGA board Smiley
HardwareCollector
Jr. Member
*
Offline Offline

Activity: 96
Merit: 3


View Profile
May 07, 2018, 12:45:40 AM
 #412

If you are data center guy such as myself, then you may prefer these server cards.

Lead time is 2 weeks:
https://www.xilinx.com/products/boards-and-kits/vcu1525-p.html#hardware

I do not trust PCIe risers with $4K hardware, there are some brave souls out here.
jasemoney
Legendary
*
Offline Offline

Activity: 1554
Merit: 1005


Forget-about-it


View Profile
May 07, 2018, 01:10:26 AM
 #413

Hey nice writeup, really interested.
Wondering if Bittware or Avnet taking bitcoin for purchases?

Also if you make a bitstream for the VCU1525 is it going to be working for the XUPP3R-VU9P?

I like to do spec mining on many coins, so I'd like to have the biggest option set available (within reason).

what speed/type DDR4 in these fpga?

have you tried porting sha244 into an asic built for sha256?

$MAID & $BTC other than that some short hodls and some long held garbage.
ZaebaloRegitsa4
Newbie
*
Offline Offline

Activity: 25
Merit: 0


View Profile
May 07, 2018, 02:21:29 AM
 #414

VCU1525 card is the Development Kit! This is not mass produced. And it can not ramp up production.
whitefire990
Copper Member
Member
**
Offline Offline

Activity: 165
Merit: 84


View Profile
May 07, 2018, 03:09:04 AM
 #415

VCU1525 card is the Development Kit! This is not mass produced. And it can not ramp up production.

I had a conference call with Xilinx before announcing this project and they agreed to transition the VCU1525 into a production product for a slightly higher price; the production version will be released in June/July, in much higher quantities.

Regarding the question about bitstream compatibility, the answer is no, a bitstream built for VCU1525 will not work on the XUPP3R.  The clock & USB UART are on different pins, so I must 'build' two versions of the bitstream, one for each card.  Although the change in the code is tiny, it still takes the tools 5+ hours to re-run place & route, with multiple runs needed to get a success.

arielbit
Legendary
*
Offline Offline

Activity: 2016
Merit: 1006


View Profile
May 07, 2018, 03:34:56 AM
Last edit: May 07, 2018, 03:45:21 AM by arielbit
 #416

great! let the FPGA manufacturers take a nice slice of the pie...the more the merrier  Cheesy

so where can i buy?...looking forward in making a rig out of these..

you make the firmware for different algos that can be loaded to FPGA..and we mine with a fee..

anything i missed?

...

do people who know c language and assembly language, who have experience in programming micro-controllers like zilog, atmel and pic ....can easily adapt to using this? like doing the stuff  that you are doing? create firmware for this FPGAs

the lack of developers in this arena and the lesser utility/other uses of FPGA (in general population) makes me think twice in investing more in this kind of stuff...unless i knew a guy in person that i can work with, not just some random guy in the internet..


DigitalCruncher
Jr. Member
*
Offline Offline

Activity: 59
Merit: 1


View Profile
May 07, 2018, 03:41:24 AM
 #417


Regarding the question about bitstream compatibility, the answer is no, a bitstream built for VCU1525 will not work on the XUPP3R.  The clock & USB UART are on different pins, so I must 'build' two versions of the bitstream, one for each card.  Although the change in the code is tiny, it still takes the tools 5+ hours to re-run place & route, with multiple runs needed to get a success.


Can you inplement a double set of interfaces to support both boards by the single firmware?
BUFGMUX_CTRL can be used to select the clock signal, if clocking assignment is different.
It is probably possible to build one firmware for both board.
whitefire990
Copper Member
Member
**
Offline Offline

Activity: 165
Merit: 84


View Profile
May 07, 2018, 04:01:27 AM
 #418


Regarding the question about bitstream compatibility, the answer is no, a bitstream built for VCU1525 will not work on the XUPP3R.  The clock & USB UART are on different pins, so I must 'build' two versions of the bitstream, one for each card.  Although the change in the code is tiny, it still takes the tools 5+ hours to re-run place & route, with multiple runs needed to get a success.


Can you inplement a double set of interfaces to support both boards by the single firmware?
BUFGMUX_CTRL can be used to select the clock signal, if clocking assignment is different.
It is probably possible to build one firmware for both board.

I get the general idea but I still have a hard time seeing how to do that with the USB-UART pins.

As far as 'resale' of these FPGA cards, there is also a tremendous future for AI mining.  In fact, if tens of thousands of people were mining crypto with these boards, and an AI mining server became available, they are so powerful that you might end up with a 'Skynet' type superintelligence, or the Kurzweil 'singularity' event. 

My point is that if, for some reason, mining crypto became unprofitable, someone could re-sale access to the FPGA hardware for AI, weather prediction or any other compute-heavy tasks.

senseless
Hero Member
*****
Offline Offline

Activity: 1118
Merit: 541



View Profile
May 07, 2018, 04:14:14 AM
Merited by suchmoon (1)
 #419

Both the VCU1525 and XUPP3R have a circuit that will shut down the FPGA power supply if the temperature exceeds limits.  This doesn't prevent you from trying to pull too much current for a short time though.

Another important note for people considering this hardware.  The VCU1525 has a fixed core voltage of 0.85V.  The XUPP3R from Bittware is more flexible and you can change the core voltage from 0.74V to 1.11V, which allows a much greater flexibility in terms of over-clocking the FPGA.  For memory intensive algorithms, a higher voltage will produce faster hash rates, vs. for power limited algorithms, a lower voltage would likely produce better hash rates.

The VCU1525 is also only 160A vccint... Increasing the voltage lowers amperage and allows you to use more power... But, I'm not sure the amperage of supply capacity the bittware board has... Happen to have a product manual on you? If the board is only designed for 100A, wouldn't do you much good even operating at 1V. I've got a couple VCU118's here that I picked up long before the VCU1525 was announced or released. Those are limited to like 80A vccint  Cry and they're damn near twice the price.

Went and tried to find the max amp on the XUPP3R and no data was available. Best I've been able to figure out is that you're limited to 75W on the 6 PIN aux and 75W on the PCI-E. This would be less than the VCU1525 which has 8 pin (150W) plus PCI-E (75W). Even if you're running at 1.1V, the max amps you could pull for the XUPP3R is 136A. Do NOT buy the XUPP3R for mining. Even with variable core voltage it's power supply is shite compared to the VCU1525. Even the VCU1525 at 160A, is quite limited in the maximum amount of 'things' you can have on in the FPGA at one time. You'll hit over 150A 0.85v using only 70% of the logic with all memories powered down.


DigitalCruncher
Jr. Member
*
Offline Offline

Activity: 59
Merit: 1


View Profile
May 07, 2018, 04:19:45 AM
 #420


Regarding the question about bitstream compatibility, the answer is no, a bitstream built for VCU1525 will not work on the XUPP3R.  The clock & USB UART are on different pins, so I must 'build' two versions of the bitstream, one for each card.  Although the change in the code is tiny, it still takes the tools 5+ hours to re-run place & route, with multiple runs needed to get a success.


Can you inplement a double set of interfaces to support both boards by the single firmware?
BUFGMUX_CTRL can be used to select the clock signal, if clocking assignment is different.
It is probably possible to build one firmware for both board.

I get the general idea but I still have a hard time seeing how to do that with the USB-UART pins.

As far as 'resale' of these FPGA cards, there is also a tremendous future for AI mining.  In fact, if tens of thousands of people were mining crypto with these boards, and an AI mining server became available, they are so powerful that you might end up with a 'Skynet' type superintelligence, or the Kurzweil 'singularity' event. 

My point is that if, for some reason, mining crypto became unprofitable, someone could re-sale access to the FPGA hardware for AI, weather prediction or any other compute-heavy tasks.



Suppose you have 2 different sets of pins.
RXD_BITTWARE and TXD_BITTWARE is one set,  RXD_XILINX and TXD_XILINX is another set.
The uart module inside FPGA has RXD input and TXD output also.
Then make connections as follows:
TXD_BITTWARE = TXD
TXD_XILINX  = TXD

RXD = RXD_BITTWARE  &  RXD_XILINX
The merging function varies between "or, xor, and" and  it is depending on internal or external pulling unconnected pins up or down.


Pages: « 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 [21] 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 ... 100 »
  Print  
 
Jump to:  

Sponsored by , a Bitcoin-accepting VPN.
Powered by MySQL Powered by PHP Powered by SMF 1.1.19 | SMF © 2006-2009, Simple Machines Valid XHTML 1.0! Valid CSS!