Can anyone tell me what chip is used in BFL single?

[eldentyrell]

After a little bit of reading, I found that protecting the JTAG port of an Altera FPGA seems to be a standard feature.

In Cyclone III LS FPGAs, the native state of JTAG is restricted to only those
instructions required for compliance to the IEEE specification.

IDCODE is "required for compliance to the IEEE specification" so this won't affect it.

Warning: TDO seems to be stuck at 1

Try setting the TCK frequency to something absurdly low ("frequency 1000" in urjtag).

If nothing changes, then you're probably right that:

they may have just switched the pins around on JTAG2. Who knows. If it would be me trying to protect my design, I'd do that too.

You'll have to try different pin hookups, but it's not as bad as it sounds.  The first step is to find out which (if any) of the 10 pins has a driver on it; that's TDO.  Then, for each of the remaining nine pins try wiggling them one at a time to figure out which one is TCK.  Then all you need is TMS.  You can get the IDCODE readout without TDI.

Don't forget to email eldentyrell and ask for your 5 BTC.

I'll definitely pay up if/when he posts an IDCODE readout from the JTAG2 chain; right now all we know is that the board isn't hooked up properly (which might be due to BFL choosing a funky pinout).

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[bulanula]

Come on, we all know ATMEL is not the FPGA chip that does the hashings but just a side ASIC used for USB or something ...

[seriouscoin]

Come on, we all know ATMEL is not the FPGA chip that does the hashings but just a side ASIC used for USB or something ...

Just Shut the fck up and get out of this forum. Loser

[||bit]

Does anyone here understand what is delivered by Amtel with this service or product? An FPGA chip or a kind of hybrid?

http://www.atmel.com/products/Other/fpga_conversion_ulc/default.aspx

[abeaulieu]

Does anyone here understand what is delivered by Amtel with this service or product? An FPGA chip or a kind of hybrid?

http://www.atmel.com/products/Other/fpga_conversion_ulc/default.aspx

Interesting. Sounds like the product is more similar to an ASIC. Probably VERY costly though since the design/conversion is handled entirely by Atmel.

[ionbasa]

http://www.atmel.com/products/Wireless/wifi/avr_xmega.aspx
hmm, how many pins are on the chips in the bfl single?

[rjk]

Does anyone here understand what is delivered by Amtel with this service or product? An FPGA chip or a kind of hybrid?

http://www.atmel.com/products/Other/fpga_conversion_ulc/default.aspx

Interesting. Sounds like the product is more similar to an ASIC. Probably VERY costly though since the design/conversion is handled entirely by Atmel.

It's the same thing as Xilinx Easy-Path, Altera Hardcopy, etc. Also known as sASIC.

[bombo999]

http://www.atmel.com/products/Wireless/wifi/avr_xmega.aspx
hmm, how many pins are on the chips in the bfl single?

If you have your own single, just look yourself.  If you don't have your own single, why do you care?

[enmaku]

As discussed, they are almost certainly using a cheap source of old-gen 65nm FPGAs: https://bitcointalk.org/index.php?topic=66314.msg769355#msg769355

Assuming this topic is correct, does anyone happen to have a source of MTBF/MTTF/FIT data for those chips?

It's rough trying to factor cost of replacement into operating costs when you have zero data on how often they'll need replaced

[rjk]

As discussed, they are almost certainly using a cheap source of old-gen 65nm FPGAs: https://bitcointalk.org/index.php?topic=66314.msg769355#msg769355

Assuming this topic is correct, does anyone happen to have a source of MTBF/MTTF/FIT data for those chips?

It's rough trying to factor cost of replacement into operating costs when you have zero data on how often they'll need replaced

That quote is a bit out of date. Due to recent comments by BFL, it appears to be more likely that they have actually produced something custom, possibly a specialized programmable ASIC (I.E., an FPGA of their own). It is becoming less likely that is is actually an off-the-shelf product.

[ionbasa]

http://www.atmel.com/products/Wireless/wifi/avr_xmega.aspx
hmm, how many pins are on the chips in the bfl single?

If you have your own single, just look yourself.  If you don't have your own single, why do you care?

I don't have one which is why I was asking. The reason I care is because this thread is to help identify the chips used in the BFL Single, I like many others are curious and would want to know what chips are used.

[enmaku]

As discussed, they are almost certainly using a cheap source of old-gen 65nm FPGAs: https://bitcointalk.org/index.php?topic=66314.msg769355#msg769355

Assuming this topic is correct, does anyone happen to have a source of MTBF/MTTF/FIT data for those chips?

It's rough trying to factor cost of replacement into operating costs when you have zero data on how often they'll need replaced

That quote is a bit out of date. Due to recent comments by BFL, it appears to be more likely that they have actually produced something custom, possibly a specialized programmable ASIC (I.E., an FPGA of their own). It is becoming less likely that is is actually an off-the-shelf product.

So it's looking less likely that we'll actually get time-to-failure data on the chips unless BFL does the testing themselves and released numbers.

[rjk]

As discussed, they are almost certainly using a cheap source of old-gen 65nm FPGAs: https://bitcointalk.org/index.php?topic=66314.msg769355#msg769355

Assuming this topic is correct, does anyone happen to have a source of MTBF/MTTF/FIT data for those chips?

It's rough trying to factor cost of replacement into operating costs when you have zero data on how often they'll need replaced

That quote is a bit out of date. Due to recent comments by BFL, it appears to be more likely that they have actually produced something custom, possibly a specialized programmable ASIC (I.E., an FPGA of their own). It is becoming less likely that is is actually an off-the-shelf product.

So it's looking less likely that we'll actually get time-to-failure data on the chips unless BFL does the testing themselves and released numbers.

As far as we know, the chips aren't even being binned, they just assemble them, see if they meet the specs, and ship. That's would be my assumption after hearing reports of some with units that throttle when others do not, in the same environment. Anyways, I have high hopes for the larger devices.

[abeaulieu]

As discussed, they are almost certainly using a cheap source of old-gen 65nm FPGAs: https://bitcointalk.org/index.php?topic=66314.msg769355#msg769355

Assuming this topic is correct, does anyone happen to have a source of MTBF/MTTF/FIT data for those chips?

It's rough trying to factor cost of replacement into operating costs when you have zero data on how often they'll need replaced

That quote is a bit out of date. Due to recent comments by BFL, it appears to be more likely that they have actually produced something custom, possibly a specialized programmable ASIC (I.E., an FPGA of their own). It is becoming less likely that is is actually an off-the-shelf product.

So it's looking less likely that we'll actually get time-to-failure data on the chips unless BFL does the testing themselves and released numbers.

Time-to-failure data on these chips would be quite difficult considering that bitcoin mining is typically an around-the-clock activity. I don't know how you would simulate this wear on the chips other than just running them and waiting until one fails, which hopefully won't be soon...

[terrytibbs]

https://bitcointalk.org/index.php?topic=79825.0

[eldentyrell]

I'll definitely pay up if/when he posts an IDCODE readout from the JTAG2 chain; right now all we know is that the board isn't hooked up properly (which might be due to BFL choosing a funky pinout).

The IDCODE readout has been found and the bounty has been paid:

  https://bitcointalk.org/index.php?topic=79825.msg886013#msg886013