I showed the paper to an ASIC designers and the reply was:
"Dual-rail domino logic is glitchy and fickle as f**k, and needs only the slightest excuse (e.g. you put a domino module next to another one) not to work. Clockless logic is interesting, but it's virtually impossible to debug it once you've got your silicon. You could build the chips, and spend a decade debugging and still have no idea what went wrong"
That guy must be a moron. People have been designing domino logic for 20+ years. It's has some special requirements, but those are not hard to meet if you know what you are doing.
I know eldentyrell, and this paper is legit. I'm proud of him, this is an excellent result for which he should be proud. This kind of thing is
real engineering; it's so nice to see this kind of result vs. the uninspired standard-cell crapola that everyone else churns out.