Xeon Phi

[cmg5461]

Yeah, that's why their Tesla stuff shows up in pretty much all of the new supercomputer builds these days, right? 

their high end tesla's kick some major ass.

[multi#lord]

Probably covered some of the stuff in thread, but interesting read on the Xeon Phi:

http://vr-zone.com/articles/intel-xeon-family-finally-accepts-the-larrabee-in-xeon-phi-and-its-futures/16361.html

[rjk]

Probably covered some of the stuff in thread, but interesting read on the Xeon Phi:

http://vr-zone.com/articles/intel-xeon-family-finally-accepts-the-larrabee-in-xeon-phi-and-its-futures/16361.html

Interesting!

The 50+ simple two-way in-order Pentium (yes, 1995 Pentium!) like cores feed the same number of 512-bit wide SIMD FP units, with the ability to deliver around 1 TFLOPs peak in double precision at around 1 GHz.

[cmg5461]

And, at least behind the closed doors, both AMD and Nvidia GPUs have been shown booting Linux on their own, without requiring a CPU.

umm. wat

[rjk]

And, at least behind the closed doors, both AMD and Nvidia GPUs have been shown booting Linux on their own, without requiring a CPU.

umm. wat

True story, but only in the hands of the engineers that designed them, no one else that I know of has been able to make it happen.

[cmg5461]

True story, but only in the hands of the engineers that designed them, no one else that I know of has been able to make it happen.

ah.  I never knew it was possible.  I guess you could think of a gpu as a slower cpu.  It must need a heavily modifies kernel though

[crazyates]

True story, but only in the hands of the engineers that designed them, no one else that I know of has been able to make it happen.

ah.  I never knew it was possible.  I guess you could think of a gpu as a slower cpu.  It must need a heavily modifies kernel though

Still. Gentoo on an APU is gonna be awesome come 2015!

Architecture:
[ ] x86
[ ] amd64
[X] opencl
[ ] arm

[DiabloD3]

And, at least behind the closed doors, both AMD and Nvidia GPUs have been shown booting Linux on their own, without requiring a CPU.

umm. wat

AMD's Fusion is a product of years of research. AMD "demo'ed" an all HyperTransport Radeon about a year after they bought ATI, and they've also been showing off prototype Fusions that don't just have Radeon pipes on-die* but usable from the x86 interface side, although what "usable" means is still up in the air, but if they've managed to use them as the backend for SIMD instructions (ie, no more dedicated FPU units, and the x86 instruction scheduler issues as many ops as it can in parallel (instead of just, say, 2 per core), instead 512 Radeon ALUs across the entire CPU) this could mean a huge goddamned increase in FP performance without needing a dedicated HAL API like OpenCL.

* On-die Fusion Radeons don't have a Radeon memory controller and natively speak HyperTransport. The up side is, they have direct access to system memory as a native processor and can access stuff directly out of on-die cache: this means you have basically zero wait time to send stuff to the GPU for processing and you have zero cost cache coherency.

[crazyates]

And, at least behind the closed doors, both AMD and Nvidia GPUs have been shown booting Linux on their own, without requiring a CPU.

umm. wat

AMD's Fusion is a product of years of research. AMD "demo'ed" an all HyperTransport Radeon about a year after they bought ATI, and they've also been showing off prototype Fusions that don't just have Radeon pipes on-die* but usable from the x86 interface side, although what "usable" means is still up in the air, but if they've managed to use them as the backend for SIMD instructions (ie, no more dedicated FPU units, and the x86 instruction scheduler issues as many ops as it can in parallel (instead of just, say, 2 per core), instead 512 Radeon ALUs across the entire CPU) this could mean a huge goddamned increase in FP performance without needing a dedicated HAL API like OpenCL.

* On-die Fusion Radeons don't have a Radeon memory controller and natively speak HyperTransport. The up side is, they have direct access to system memory as a native processor and can access stuff directly out of on-die cache: this means you have basically zero wait time to send stuff to the GPU for processing and you have zero cost cache coherency.

This is an old slide, but it gives a good vision of AMD's overall goal. We are somewhere between step 2 and step 3, and it's only going to be getting better! AMD has one of the most creative and innovative visions for the future of consumer computing (as opposed to intel just shrinking nm die sizes), and I  think it's progressing quite well (just look at the success of their APU sales) I also think it's only going to get better for them as they move along with even more amazing features like what you just described.

/amdfanboyrant

[DiabloD3]

And, at least behind the closed doors, both AMD and Nvidia GPUs have been shown booting Linux on their own, without requiring a CPU.

umm. wat

AMD's Fusion is a product of years of research. AMD "demo'ed" an all HyperTransport Radeon about a year after they bought ATI, and they've also been showing off prototype Fusions that don't just have Radeon pipes on-die* but usable from the x86 interface side, although what "usable" means is still up in the air, but if they've managed to use them as the backend for SIMD instructions (ie, no more dedicated FPU units, and the x86 instruction scheduler issues as many ops as it can in parallel (instead of just, say, 2 per core), instead 512 Radeon ALUs across the entire CPU) this could mean a huge goddamned increase in FP performance without needing a dedicated HAL API like OpenCL.

* On-die Fusion Radeons don't have a Radeon memory controller and natively speak HyperTransport. The up side is, they have direct access to system memory as a native processor and can access stuff directly out of on-die cache: this means you have basically zero wait time to send stuff to the GPU for processing and you have zero cost cache coherency.

This is an old slide, but it gives a good vision of AMD's overall goal. We are somewhere between step 2 and step 3, and it's only going to be getting better! AMD has one of the most creative and innovative visions for the future of consumer computing (as opposed to intel just shrinking nm die sizes), and I  think it's progressing quite well (just look at the success of their APU sales) I also think it's only going to get better for them as they move along with even more amazing features like what you just described.

/amdfanboyrant

Yeah, what I described is clearly Step 3 or later. Intel also seems to have finally sold a "step 3" type of device in the Phi, depending on what it actually can do.

[crazyates]

Yeah, what I described is clearly Step 3 or later. Intel also seems to have finally sold a "step 3" type of device in the Phi, depending on what it actually can do.

Intel seems more interested in incorporating the CPU into the GPU, while AMD is incorporating the GPU into the CPU. Totally different mindsets/endgames/results.

[AzN1337c0d3r]

But if it still can perform just as well on highly branchy code, I might have a use for one of those.

That would make it crazy awesome for raytracing.

Yeah, that's why their Tesla stuff shows up in pretty much all of the new supercomputer builds these days, right?  

their high end tesla's kick some major ass.

On the wallet maybe. Last I checked, a Tesla M2090 was north of $4000.

Also 1 TFLOP is not that impressive. HD7970 is 947 DP GFLOP and it was released in January and doesn't have access to Intel's 22 nm 3D tri-gate tech.

[DiabloD3]

Yeah, what I described is clearly Step 3 or later. Intel also seems to have finally sold a "step 3" type of device in the Phi, depending on what it actually can do.

Intel seems more interested in incorporating the CPU into the GPU, while AMD is incorporating the GPU into the CPU. Totally different mindsets/endgames/results.

They both want branch/loop happy highly parallel computation. The Radeon's biggest "problem" (and I'm using the term loosely) is that wavefronts are ran in lockstep: both sides of a branch are the same length, even if it requires inserting no-ops, and loops that have lengths that are set at runtime (instead of static/compile time set) are just as nasty.

CPUs, otoh, can't do highly parallel calculations because of all the hardware dedicated dealing with branching, branch prediction, cache prediction, etc etc etc takes up a lot of room, produces a lot of heat, and uses a lot of power. I wonder how much stuff Intel removed to put 50 cores on a card.

[goxed]

I wonder how much stuff Intel removed to put 50 cores on a card.

Here's a pdf depicting the organization of Larrabee, the precursor of Phi.
http://users.ece.gatech.edu/lanterma/mpg08/Larrabee_ECE4893.pdf

[DiabloD3]

I wonder how much stuff Intel removed to put 50 cores on a card.

Here's a pdf depicting the organization of Larrabee, the precursor of Phi.
http://users.ece.gatech.edu/lanterma/mpg08/Larrabee_ECE4893.pdf

Im already well aware of how they designed that. Its more butchered than Atom. But from what I've heard, Phi isn't nearly as bad.

[Gabi]

Also 1 TFLOP is not that impressive. HD7970 is 947 DP GFLOP and it was released in January and doesn't have access to Intel's 22 nm 3D tri-gate tech.

Protip: Xeon Phi run x86 code

Good luck using the 7970 (or nvidia) computing power, having to fight with opencl and cuda.

[Gabi]

Probably covered some of the stuff in thread, but interesting read on the Xeon Phi:

http://vr-zone.com/articles/intel-xeon-family-finally-accepts-the-larrabee-in-xeon-phi-and-its-futures/16361.html

This article fail:

So, how does it stand performance wise? Its double precision FP throughput is the same as the typical AMD Radeon HD7970 card which costs one quarter of the amount but with much smaller memory, 3 GB, and no ECC.

No ECC? The 7970 has ECC 

[rjk]

The 7970 has ECC  

Are you sure? That's usually reserved for the expensive enterprisey cards like FirePro.

[DiabloD3]

Probably covered some of the stuff in thread, but interesting read on the Xeon Phi:

http://vr-zone.com/articles/intel-xeon-family-finally-accepts-the-larrabee-in-xeon-phi-and-its-futures/16361.html

This article fail:

So, how does it stand performance wise? Its double precision FP throughput is the same as the typical AMD Radeon HD7970 card which costs one quarter of the amount but with much smaller memory, 3 GB, and no ECC.

No ECC? The 7970 has ECC 

No it doesn't. What GCN did was add ECC to all internal on-die memory (caches, local stores, etc), but the only cards AMD has that have ECC GDDR5 are FirePro/FireStream cards, and although they're normal GCN chips, they're not referred to as such.

[multi#lord]

I was also under the impression the 7970 did have ECC, but I thought it was not used. It would cost performance? My impression is based from some articles and postings such as the two below.

I read this sometime back on: http://www.anandtech.com/Show/Index/4455?cPage=4&all=False&sort=0&page=6&slug=amds-graphics-core-next-preview-amd-architects-for-compute

Finally on the memory side, AMD is adding proper ECC support to supplement their existing EDC (Error Detection & Correction) functionality, which is used to ensure the integrity of memory transmissions across the GDDR5 memory bus. Both the SRAM and VRAM memory can be ECC protected. For the SRAM this is a free operation, while for the VRAM there will be a performance overhead. We’re assuming that AMD will be using a virtual ECC scheme like NVIDIA, where ECC data is distributed across VRAM rather than using extra memory chips/controllers.

Shamino has done some LN2 overclocking when the 7970 was released, in his forum he wrote for the 7970,

actually 1800 ram is easy, i ran 2000 ram and it got the ECC correction and the score was worse.

http://kingpincooling.com/forum/showthread.php?t=1559