Bitcoin Forum

Taken from:

https://products.butterflylabs.com/65nm-asic-bitcoin-mining-chip.html



https://products.butterflylabs.com/media/catalog/product/cache/1/image/9df78eab33525d08d6e5fb8d27136e95/b/f/bfl_asics.1024px.jpg



65 nm ASIC Mining Chip
4 GH/s Calculation Speed


Specifications:


    Technology: Global Foundries advanced 65nm technology (IBM core)

    Die size: 7.5 x 7.5 mm

    Substrate package: 10 x 10 mm

    Package type: Standard BGA 144

    Design type: 100% Hand routed for performance density

    Power consumption: 3.2 Watt per GH/s

    Performance: 4 GH/s

    Performance design: 16 engines @ 250mhz nominal (294mhz max)


Advantages of Butterfly Labs chips:


    1/2 the power usage per GH as the closest competitor

    1/10th the silicon area per GH as the closest competitor (Very high performance density)

    Proven design currently operating in the field and ready to go.

    Unlike some QFN packages which require underside heat sinks, you can use off the shelf heat sinks due to the FCBGA package. No need to design and manufacture heat sinks!


Terms of purchase:


    Delivery:  100 days

    Payment:  50% deposit on order and 50% upon delivery

    Cancellation:  All sales are final and deposits will not be returned if final payment is not made prior to delivery.

    Minimum purchase:  100 chips


Considerations:


    Chip grades:  Chips come in four grades of performance.  Chips are sold in mixed grade lots.  A grade has 16 engines, B grade has 15 engines, C grade has 14 engines and D grade has no less than 12 engines.  All chips run at a minimum of 250 mhz.  Higher grade chips will run up to 294mhz.  The percentage distribution in each lot is 60% Grade A, 20% Grade B, 15% Grade C and 5% Grade D.

    Reference documentation:  Butterfly Labs is releasing it's PCB schematics & MCU code to open source.  Links to this documentation will follow shortly.

    Limited availability:  Chip availability is limited to 100,000 units.

https://www.youtube.com/watch?v=YhsKCnDD3F8 chip production

Bullshit. They should change the supplier.

Global Foundries are the world's second largest independent  semiconductor foundry. It use to be called AMD if you remember that little company, they sold off their fab which became Global Foundries, they are not noobs.

They must have found the shittiest design and verification engineers on the planet to get such low performance from a full custom 65nm asic.  Further, for a chip with such little logic on it their yields are crap.

My guess would be they used shitty engineers and global foundaries' standard cell library, the engineers didn't setup their simulations correctly and as such the cores fail under even the slightest real world heat.  This guess is additionally backed up by the high hardware error to accepted rates posted in screenshots by various Jalapeno recipients.   I would guess that the estimated hash rate on the pool side is much lower than the promised 5 gh/s.

12 posts and already trolling, what's the name of your other account?

No other account.  Just someone who is familiar with IC design and thinks such a small chip (7.5mm^2) consisting of no more than 16k 32-bit adders on a process that yields such low clock rates (for example see: http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=4253311) and high defect rates (to quote from your original link: "A grade has 16 engines, B grade has 15 engines, C grade has 14 engines and D grade has no less than 12 engines.  All chips run at a minimum of 250 mhz.  Higher grade chips will run up to 294mhz.  The percentage distribution in each lot is 60% Grade A, 20% Grade B, 15% Grade C and 5% Grade D.").

If the error rate was this high, a single 300mm wafer would be luckly to yield one working consumer graphics card.

Do you care to speculate what could be the specific mistake that the BFL's designers made?

For example eldentyrell speculated a while back that they made their simulations at the default temperature chosen by SPICE in absence of specific setting: 25 deg C.

https://bitcointalk.org/index.php?topic=166321.0

Obviously, we don't have sufficient information to make a real assesment; but I think even making a scientific wild ass guess will have some educational value for the readership of this forum.

erk no one wants your employers piece of shit chips...from piece of shit humans ....so take your shit and go home sock puppet

BFL think people are stupid.

First turn in their orders. If your chips are like their minrigs of 1500ghs. Take more than a year to deliver.
Performance will be a third of what was promised. But will offer a performance boost payment.  How much more they can milk the cow?

I would guess that when doing integrity simulations they did not set the upper bound to say 85C, which is fairly common in commercial electronics.  In applications that use heatsinks sometimes this results in incorrectly calculating the efficiency of said heatsink.   This can be empirically tested, say by cooling with LN2, which is readily available at most lab test supply shops.  If the chip error rate reduces at the same clock frequency, then the efficiency of the heatsink and/or upper bound of simulation was not 85C.  In Cadence's package design software and subsequent sim, -20C and 85C are used as the lower and upper bounds, respectively.

There are a number of other reasons they could be experiencing low yields, but the facts are a) Global Foundaries' 65nm process is fairly mature b) the design rule checks (DRC's) provided by foundaries and/or built into any usable EDA software would catch the majority of other potential culprits, such as signal integrity or cross talk issues.

Agreed, insanely low yields, plus several design iterations suggests incompetent development engineers. Also this:


I've been out of the biz a long time now, but why the claim that perfect chips clock faster than defective chips? I suppose they could be accounting for parasitic power consumption of defective cores limiting the clock rate to keep power dissipation down, but then what are they going to do with the <250MHz parts? And have they fully characterised their dodgy design? It would be embarrassing if the yield/speed varies hugely between batches. Oh and up to, I always mentally translate that as less than.

If they used fully unrolled SHA256 pipelines (128+ stages), a single glitch anywhere would take out an entire engine. If each engine takes up 0.5mm and one glitch would wreck it, that could explain crappy yields.

Good point, though yields still should not be that crappy. Interestingly Bitfury's new chip is using 756 rolled double-cores https://bitcointalk.org/index.php?topic=228677.msg2408299#msg2408299

0.5 (mm2) is still a lot of real estate you need to get perfect in order for 1 engine to function. It might stretch the boundaries of the process.
Bitfury's method is a lot more resistant to failure. If you lose a few cores out of 756, nobody cares. Just have the firmware test em on initial and mark em dead if they don't test right.

I don't think he does (the comms protocol seems pretty basic). But you probably don't have to as bad cores will mostly just produce bad hashes, which can just be filtered out in the mining software (I assume the current miners check the nonces before submitting them to a pool, its a low cost operation to do just for the winning shares).

Of course one defect in a pipeline wrecks the pipeline.  Sorry if I assumed it was obvious, but it is.   However, for such a high defect per area density, modern commercial CPU and GPU manufacture would be lucky to yield one working chip per 300mm wafer.   GPU's would cost > 10k USD.

Personally I think rolled cores are a wise decision as he should yield slightly less performance per area assuming ideal situations and higher when defects are throw into the equation.  The advantages of constant folding for the ternary addition required for SHA256 are relatively minimal when you leave the realm of FPGAs/structured ASICs.   ASIC perf/cost centers around usable area at the end of the day.  That is unless your goal is to make some really fancy glass.

I was just reverse engineering the 7950/7970 die size (352mm2) with their binning. Roughly 45x the die size and they disable 256 of the cores during binning. It didn't seem unlikely that 50-100 of those cores underperform or fail tests. But I was just doing back of the envelope calculations. I might be able to lay my hands on what sort of defect rate AMD actually sees at that die size and what their worst case scenario looks like.

Might be interesting for comparison purposes, but I realize a GPU of that size is a "whole nother critter".  ;D

Many people have speculated (Avalon themselves as well) that it's not actually a 65nm chip

BFL are showing some entrepreneurial initiative.
By selling chips, building on Avalon's approach by only asking half up front is an improvement, and shows a more attractive approach  for purchasing, than what Avalon offered.(they would have to, not being the first) 
Simple business model with good cashflow and margin built in with much less overhead - it makes sense.
It is difficult for a buisness to thrive with negative cashflow. This is exacerbated by negative customer sentiment, and can lead a buisness into a money losing spiral. To see BFL adapting to the market and making new offers is encouraging, as it provides competition to the encumbent monopoly of Avalon, and adds diversity to the emerging ASIC embedded platforms under development.
Hopefully it will allow BFL to survive longer, and grow as a business, and finally discover the benefits of looking after their customers.

Avalon is a monopoly like the GPL is a monopoly

BFL should release Reference documentation for people to acquire more information of the chip application.

Funny. IF those are Global Foundries chips... why did they ever wait for shipments from China? GF has manufacturing plants in Germany, Singapore and Saratoga, NY. None in China.

They did not?

To be honest, none of those places other than NY have particularly faster transit times for ocean freight due to the INSANE volume going from China to the US. Its like a mail box that gets collected by the mail man every 5 minutes.

I must have been mistaken then. Somehow, I have often read that they were waiting for shipments from China...

And Germany to US, with an express mailing service, insured, takes around 24 hours if you consider UPS or FEDEX. They are insanely fast, if you want it. And if I was BFL... I'd want that ;)

I think some people were speculating that BFL used TSMC which is in Taiwan.

One mistake in your proposition is to assume that the delivered 'mix' is a fair representation of the yield.
I think BFL is perfectly capable of keeping a significant portion of the grade A chips for themselfs.
They (will) have many products to support and i can easily imagine they don't want to put lower grades in their devices. They also made promises to their customers about hashrtes and power so they actually need the higher grade chips.
So it would seem natural for them to want to sell off as much of the lower grades as possible.
So i don't think we can say anything about their actual yield of grade A chips.

Considering the ASIC's haven't even been ordered yet, as BFL are still ascertaining the final numbers before they pace the order, you have no idea what the yield will be. The process might have improved dramatically since the last wafers. They may not be able to deliver the low grade chips in volume.

I don't think that too little high grade chips will be a problem.

They may have a botched wafer that has a bugged design on it with almost no grade A chips from the yield.
They could mix that with a fixed wafer to somewhat recoup the costs of the bad one.

It explains why they would have money problems though, GF isn't really the "cheapest" place. They are among the best, though.

They got at least $7million in pre-order payments if you can believe http://bfl.ptz.ro/ which I don't.

Is that what you call money problems?

Then they should have hired professionals to do their design work for them in the first place. Actually they could do it right now, and maybe get a good second-gen product out of the door before they lose too many customers. Or perhaps Josh is just looking to buy an island using the pre-order stash?

That all depends on how much of that they have spent. According to BFL, they have spent none of the pre-order money they have.
Expensive chips eat into margins, which just doubled for BFL when they had to go from 1 chip Jalapeno's to 2 chips.

Loose customers yeah lol, like the 7million came from thin air did it?  I would say they have at least 7mill worth of customers.
The ASIC is designed, they work, and they are shipping fast. If you are trying to make a point about some other ASIC they may make in the future fair enough, if not then I suspect you are just trolling. The latter is more likely from the tone of your BS.

Yup, trolling. But then you're shilling. I'm new here and I thought it was about time I lost the Mr Nice Guy facade and tried out my darker instincts. But it is my honest opinion of BFL. Nice to rattle your cage  ;D BTW its lose, not loose (though some of their customers might be getting a bit loose in the bowel department given all the delays and shenanigans).

Yes. With 10 estimated employees, 4-5 million dollars in costs towards development through subcontractors, I call it money problems.


10 employees at around 25-30k if they are not so well paid, makes for another 360.000. Lets say they burnt the first batches of chips, blew a lot of cases.... blew lots of chips, have to pay health insurance. Another 300.000.

I have calculated an ASICs business, since I have no idea what to do there. I called up contractors and specialists for everything, since I thought if BFL makes millionaires, why not become one myself?

As it turned out, some of the more prestigious development companies asked between 1.5 and 2 million EURO in advance for initial development and estimated a timeframe of one to two years until serial production could start.


 

^^This^^
is precisely why I am concerned about BFL's pre-order money.
If they have used the pre-order money to fund their ASIC development (which has run over budget on both time and money), then BFL customers have to hope that they don't get hit by a wave of refunds and that the pre-order cash keeps rolling in.
If they have not used the pre-order money (unlikely imo) then how did they fund the $4-5 million in operating costs up to this point?

Of course you wouldn't have a clue. This is utter BS. you don't know about investors or revenue from their FPGA sales or nothing about them, it's just a really obvious smear attempt.

Most of the pre-orders were placed after the the wafers and design were done, which kind of blows your revenue wild guesses.

You can infer profit margins from BFL's FPGA equipment because it is all made from off off the shelf equipment and the cost of the components are well known.

BFL has never disclosed any venture capital investments made in their company, so that is a big red flag and a concern to anyone considering investing via pre-order in BFL.

These are serious concerns about how BFL can continue to fund their operating costs without dipping into pre-order funds. And if they are dipping into pre-order funds, it is even more concerning because they are lying about not doing so.

93% of BFL's order base in dollar terms is in non-Jalepeno units, and they have only shipped 10% of their Jalapeno units. That is 10% of $490,000 which is $49,000 in revenue over the last 2 months. How much of that (if any) is profit is also concerning, since all those orders were priced with 1 $90 (retail) chip but ships with 2.

Instead of re-assuring investors with pre-orders by supplying actual information about their financial health, all BFL does is call people liars and douches and accuse them of smear campaigns. What are they hiding and why are they hiding it?

There are also no new info about their 50 GH/s or 25 GH/s miners. Have they exhausted all their wafers, so they prefer to ship just the Jalapenos? I can't also see a word about their trade-ins, which should cost them even more money.

There is plenty of new info on them, just not in this thread.

Citation please.

I hope this has been done through investor money. If their investors have goven them enough money, no worries. The margins on FPGAs was not very high. That is easily said since you can source all parts on digikey, even the FPGA chips.


I dont know shit about their operation, but I know the costs. I don't earn anything from a smear campaign, actually. I'd love them to have been more professional. But since I found a COO calling customers stupid cunts, I have refunded a lucrative order.

The last time I heard a CEO call someone asshole and cunts was with a pretty big other company: ENRON ;)


Also, according to the laws of the state BFL is incorporated in, they would have to disclose non-private venture capital funds. As a corporation, the only thing they have to disclose is who owns shares, in a limited manner.

So, from information policy and what I could dig up, the only way they could pull off what they have been saying is by having someone private signing a private loan to the corporation. Thats the only thing that does not leave a papertrail to follow. Or a bank loan. But sorry, never ever.


But, since you said most orders were done after the wafers were done: Interesting, that means they would have had such an amount invested at that point. Or not. Depending on what game they were actually playing.

I don't care either way, a COO calling people cunts on a public forum who argues that an engineer can tell a customer and his superior that "the project is done when it is done" is enough for me to pull my personal plug.

But, we will see. This is an interesting game of competition coming.

It is bizarre that Erk would claim that most orders were placed "after the design was done" since BFL (as of early June) has not completed the design of the ASIC Singles and Mini-rigs and had to redo the Jalapeno board (MOSFETs were the wrong spec) as late as May 25th.