BFL ASIC specifications

[erk]

Taken from:

https://products.butterflylabs.com/65nm-asic-bitcoin-mining-chip.html







65 nm ASIC Mining Chip
4 GH/s Calculation Speed


Specifications:


    Technology: Global Foundries advanced 65nm technology (IBM core)

    Die size: 7.5 x 7.5 mm

    Substrate package: 10 x 10 mm

    Package type: Standard BGA 144

    Design type: 100% Hand routed for performance density

    Power consumption: 3.2 Watt per GH/s

    Performance: 4 GH/s

    Performance design: 16 engines @ 250mhz nominal (294mhz max)


Advantages of Butterfly Labs chips:


    1/2 the power usage per GH as the closest competitor

    1/10th the silicon area per GH as the closest competitor (Very high performance density)

    Proven design currently operating in the field and ready to go.

    Unlike some QFN packages which require underside heat sinks, you can use off the shelf heat sinks due to the FCBGA package. No need to design and manufacture heat sinks!


Terms of purchase:


    Delivery:  100 days

    Payment:  50% deposit on order and 50% upon delivery

    Cancellation:  All sales are final and deposits will not be returned if final payment is not made prior to delivery.

    Minimum purchase:  100 chips


Considerations:


    Chip grades:  Chips come in four grades of performance.  Chips are sold in mixed grade lots.  A grade has 16 engines, B grade has 15 engines, C grade has 14 engines and D grade has no less than 12 engines.  All chips run at a minimum of 250 mhz.  Higher grade chips will run up to 294mhz.  The percentage distribution in each lot is 60% Grade A, 20% Grade B, 15% Grade C and 5% Grade D.

    Reference documentation:  Butterfly Labs is releasing it's PCB schematics & MCU code to open source.  Links to this documentation will follow shortly.

    Limited availability:  Chip availability is limited to 100,000 units.

https://www.youtube.com/watch?v=YhsKCnDD3F8 chip production

[mezzomix]

   Design type: 100% Hand routed for performance density

Bullshit. They should change the supplier.

[erk]

   Design type: 100% Hand routed for performance density

Bullshit. They should change the supplier.

Global Foundries are the world's second largest independent  semiconductor foundry. It use to be called AMD if you remember that little company, they sold off their fab which became Global Foundries, they are not noobs.

[ultrix]

   Design type: 100% Hand routed for performance density

Bullshit. They should change the supplier.

They must have found the shittiest design and verification engineers on the planet to get such low performance from a full custom 65nm asic.  Further, for a chip with such little logic on it their yields are crap.

My guess would be they used shitty engineers and global foundaries' standard cell library, the engineers didn't setup their simulations correctly and as such the cores fail under even the slightest real world heat.  This guess is additionally backed up by the high hardware error to accepted rates posted in screenshots by various Jalapeno recipients.   I would guess that the estimated hash rate on the pool side is much lower than the promised 5 gh/s.

[erk]

   Design type: 100% Hand routed for performance density

Bullshit. They should change the supplier.

They must have found the shittiest design and verification engineers on the planet to get such low from a full custom 65nm asic.  Further, for a chip with such little logic on it their yields are crap.

My guess would be they used shitty engineers and global foundaries' standard cell library, the engineers didn't setup their simulations correctly and as such the cores fail under even the slightest real world heat.  This guess is additionally backed up by the high hardware error to accepted rates posted in screenshots by various Jalapeno recipients.   I would guess that the estimated hash rate on the pool side is much lower than the promised 5 gh/s.

12 posts and already trolling, what's the name of your other account?

[ultrix]

   Design type: 100% Hand routed for performance density

Bullshit. They should change the supplier.

They must have found the shittiest design and verification engineers on the planet to get such low from a full custom 65nm asic.  Further, for a chip with such little logic on it their yields are crap.

My guess would be they used shitty engineers and global foundaries' standard cell library, the engineers didn't setup their simulations correctly and as such the cores fail under even the slightest real world heat.  This guess is additionally backed up by the high hardware error to accepted rates posted in screenshots by various Jalapeno recipients.   I would guess that the estimated hash rate on the pool side is much lower than the promised 5 gh/s.

12 posts and already trolling, what's the name of your other account?

No other account.  Just someone who is familiar with IC design and thinks such a small chip (7.5mm^2) consisting of no more than 16k 32-bit adders on a process that yields such low clock rates (for example see: http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=4253311) and high defect rates (to quote from your original link: "A grade has 16 engines, B grade has 15 engines, C grade has 14 engines and D grade has no less than 12 engines.  All chips run at a minimum of 250 mhz.  Higher grade chips will run up to 294mhz.  The percentage distribution in each lot is 60% Grade A, 20% Grade B, 15% Grade C and 5% Grade D.").

If the error rate was this high, a single 300mm wafer would be luckly to yield one working consumer graphics card.

[2112]

No other account.  Just someone who is familiar with IC design and thinks such a small chip (7.5mm^2) consisting of no more than 16k 32-bit adders on a process that yields such low clock rates (for example see: http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=4253311) and high defect rates (to quote from your original link: "A grade has 16 engines, B grade has 15 engines, C grade has 14 engines and D grade has no less than 12 engines.  All chips run at a minimum of 250 mhz.  Higher grade chips will run up to 294mhz.  The percentage distribution in each lot is 60% Grade A, 20% Grade B, 15% Grade C and 5% Grade D.").

Do you care to speculate what could be the specific mistake that the BFL's designers made?

For example eldentyrell speculated a while back that they made their simulations at the default temperature chosen by SPICE in absence of specific setting: 25 deg C.

https://bitcointalk.org/index.php?topic=166321.0

Obviously, we don't have sufficient information to make a real assesment; but I think even making a scientific wild ass guess will have some educational value for the readership of this forum.

[YipYip]

   Design type: 100% Hand routed for performance density

Bullshit. They should change the supplier.

Global Foundries are the world's second largest independent  semiconductor foundry. It use to be called AMD if you remember that little company, they sold off their fab which became Global Foundries, they are not noobs.

erk no one wants your employers piece of shit chips...from piece of shit humans ....so take your shit and go home sock puppet

[titomane]

BFL think people are stupid.

First turn in their orders. If your chips are like their minrigs of 1500ghs. Take more than a year to deliver.
Performance will be a third of what was promised. But will offer a performance boost payment.  How much more they can milk the cow?

[ultrix]

Do you care to speculate what could be the specific mistake that the BFL's designers made?

For example eldentyrell speculated a while back that they made their simulations at the default temperature chosen by SPICE in absence of specific setting: 25 deg C.

https://bitcointalk.org/index.php?topic=166321.0

Obviously, we don't have sufficient information to make a real assesment; but I think even making a scientific wild ass guess will have some educational value for the readership of this forum.

I would guess that when doing integrity simulations they did not set the upper bound to say 85C, which is fairly common in commercial electronics.  In applications that use heatsinks sometimes this results in incorrectly calculating the efficiency of said heatsink.   This can be empirically tested, say by cooling with LN2, which is readily available at most lab test supply shops.  If the chip error rate reduces at the same clock frequency, then the efficiency of the heatsink and/or upper bound of simulation was not 85C.  In Cadence's package design software and subsequent sim, -20C and 85C are used as the lower and upper bounds, respectively.

There are a number of other reasons they could be experiencing low yields, but the facts are a) Global Foundaries' 65nm process is fairly mature b) the design rule checks (DRC's) provided by foundaries and/or built into any usable EDA software would catch the majority of other potential culprits, such as signal integrity or cross talk issues.

[J35st3r]

There are a number of other reasons they could be experiencing low yields, but the facts are a) Global Foundaries' 65nm process is fairly mature b) the design rule checks (DRC's) provided by foundaries and/or built into any usable EDA software would catch the majority of other potential culprits, such as signal integrity or cross talk issues.

Agreed, insanely low yields, plus several design iterations suggests incompetent development engineers. Also this:

Chip grades:  Chips come in four grades of performance.  Chips are sold in mixed grade lots.  A grade has 16 engines, B grade has 15 engines, C grade has 14 engines and D grade has no less than 12 engines.  All chips run at a minimum of 250 mhz.  Higher grade chips will run up to 294mhz.  The percentage distribution in each lot is 60% Grade A, 20% Grade B, 15% Grade C and 5% Grade D

I've been out of the biz a long time now, but why the claim that perfect chips clock faster than defective chips? I suppose they could be accounting for parasitic power consumption of defective cores limiting the clock rate to keep power dissipation down, but then what are they going to do with the <250MHz parts? And have they fully characterised their dodgy design? It would be embarrassing if the yield/speed varies hugely between batches. Oh and up to, I always mentally translate that as less than.

[k9quaint]

Do you care to speculate what could be the specific mistake that the BFL's designers made?

For example eldentyrell speculated a while back that they made their simulations at the default temperature chosen by SPICE in absence of specific setting: 25 deg C.

https://bitcointalk.org/index.php?topic=166321.0

Obviously, we don't have sufficient information to make a real assesment; but I think even making a scientific wild ass guess will have some educational value for the readership of this forum.

I would guess that when doing integrity simulations they did not set the upper bound to say 85C, which is fairly common in commercial electronics.  In applications that use heatsinks sometimes this results in incorrectly calculating the efficiency of said heatsink.   This can be empirically tested, say by cooling with LN2, which is readily available at most lab test supply shops.  If the chip error rate reduces at the same clock frequency, then the efficiency of the heatsink and/or upper bound of simulation was not 85C.  In Cadence's package design software and subsequent sim, -20C and 85C are used as the lower and upper bounds, respectively.

There are a number of other reasons they could be experiencing low yields, but the facts are a) Global Foundaries' 65nm process is fairly mature b) the design rule checks (DRC's) provided by foundaries and/or built into any usable EDA software would catch the majority of other potential culprits, such as signal integrity or cross talk issues.

If they used fully unrolled SHA256 pipelines (128+ stages), a single glitch anywhere would take out an entire engine. If each engine takes up 0.5mm and one glitch would wreck it, that could explain crappy yields.

[J35st3r]

If they used fully unrolled SHA256 pipelines (128+ stages), a single glitch anywhere would take out an entire engine. If each engine takes up 0.5mm and one glitch would wreck it, that could explain crappy yields.

Good point, though yields still should not be that crappy. Interestingly Bitfury's new chip is using 756 rolled double-cores https://bitcointalk.org/index.php?topic=228677.msg2408299#msg2408299

[k9quaint]

If they used fully unrolled SHA256 pipelines (128+ stages), a single glitch anywhere would take out an entire engine. If each engine takes up 0.5mm and one glitch would wreck it, that could explain crappy yields.

Good point, though yields still should not be that crappy. Interestingly Bitfury's new chip is using 756 rolled double-cores https://bitcointalk.org/index.php?topic=228677.msg2408299#msg2408299

0.5 (mm2) is still a lot of real estate you need to get perfect in order for 1 engine to function. It might stretch the boundaries of the process.
Bitfury's method is a lot more resistant to failure. If you lose a few cores out of 756, nobody cares. Just have the firmware test em on initial and mark em dead if they don't test right.

[J35st3r]

Bitfury's method is a lot more resistant to failure. If you lose a few cores out of 756, nobody cares. Just have the firmware test em on initial and mark em dead if they don't test right.

I don't think he does (the comms protocol seems pretty basic). But you probably don't have to as bad cores will mostly just produce bad hashes, which can just be filtered out in the mining software (I assume the current miners check the nonces before submitting them to a pool, its a low cost operation to do just for the winning shares).

[ultrix]

Do you care to speculate what could be the specific mistake that the BFL's designers made?

For example eldentyrell speculated a while back that they made their simulations at the default temperature chosen by SPICE in absence of specific setting: 25 deg C.

https://bitcointalk.org/index.php?topic=166321.0

Obviously, we don't have sufficient information to make a real assesment; but I think even making a scientific wild ass guess will have some educational value for the readership of this forum.

I would guess that when doing integrity simulations they did not set the upper bound to say 85C, which is fairly common in commercial electronics.  In applications that use heatsinks sometimes this results in incorrectly calculating the efficiency of said heatsink.   This can be empirically tested, say by cooling with LN2, which is readily available at most lab test supply shops.  If the chip error rate reduces at the same clock frequency, then the efficiency of the heatsink and/or upper bound of simulation was not 85C.  In Cadence's package design software and subsequent sim, -20C and 85C are used as the lower and upper bounds, respectively.

There are a number of other reasons they could be experiencing low yields, but the facts are a) Global Foundaries' 65nm process is fairly mature b) the design rule checks (DRC's) provided by foundaries and/or built into any usable EDA software would catch the majority of other potential culprits, such as signal integrity or cross talk issues.

If they used fully unrolled SHA256 pipelines (128+ stages), a single glitch anywhere would take out an entire engine. If each engine takes up 0.5mm and one glitch would wreck it, that could explain crappy yields.

Of course one defect in a pipeline wrecks the pipeline.  Sorry if I assumed it was obvious, but it is.   However, for such a high defect per area density, modern commercial CPU and GPU manufacture would be lucky to yield one working chip per 300mm wafer.   GPU's would cost > 10k USD.

[ultrix]

If they used fully unrolled SHA256 pipelines (128+ stages), a single glitch anywhere would take out an entire engine. If each engine takes up 0.5mm and one glitch would wreck it, that could explain crappy yields.

Good point, though yields still should not be that crappy. Interestingly Bitfury's new chip is using 756 rolled double-cores https://bitcointalk.org/index.php?topic=228677.msg2408299#msg2408299

Personally I think rolled cores are a wise decision as he should yield slightly less performance per area assuming ideal situations and higher when defects are throw into the equation.  The advantages of constant folding for the ternary addition required for SHA256 are relatively minimal when you leave the realm of FPGAs/structured ASICs.   ASIC perf/cost centers around usable area at the end of the day.  That is unless your goal is to make some really fancy glass.

[k9quaint]

Do you care to speculate what could be the specific mistake that the BFL's designers made?

For example eldentyrell speculated a while back that they made their simulations at the default temperature chosen by SPICE in absence of specific setting: 25 deg C.

https://bitcointalk.org/index.php?topic=166321.0

Obviously, we don't have sufficient information to make a real assesment; but I think even making a scientific wild ass guess will have some educational value for the readership of this forum.

I would guess that when doing integrity simulations they did not set the upper bound to say 85C, which is fairly common in commercial electronics.  In applications that use heatsinks sometimes this results in incorrectly calculating the efficiency of said heatsink.   This can be empirically tested, say by cooling with LN2, which is readily available at most lab test supply shops.  If the chip error rate reduces at the same clock frequency, then the efficiency of the heatsink and/or upper bound of simulation was not 85C.  In Cadence's package design software and subsequent sim, -20C and 85C are used as the lower and upper bounds, respectively.

There are a number of other reasons they could be experiencing low yields, but the facts are a) Global Foundaries' 65nm process is fairly mature b) the design rule checks (DRC's) provided by foundaries and/or built into any usable EDA software would catch the majority of other potential culprits, such as signal integrity or cross talk issues.

If they used fully unrolled SHA256 pipelines (128+ stages), a single glitch anywhere would take out an entire engine. If each engine takes up 0.5mm and one glitch would wreck it, that could explain crappy yields.

Of course one defect in a pipeline wrecks the pipeline.  Sorry if I assumed it was obvious, but it is.   However, for such a high defect per area density, modern commercial CPU and GPU manufacture would be lucky to yield one working chip per 300mm wafer.   GPU's would cost > 10k USD.

I was just reverse engineering the 7950/7970 die size (352mm2) with their binning. Roughly 45x the die size and they disable 256 of the cores during binning. It didn't seem unlikely that 50-100 of those cores underperform or fail tests. But I was just doing back of the envelope calculations. I might be able to lay my hands on what sort of defect rate AMD actually sees at that die size and what their worst case scenario looks like.

Might be interesting for comparison purposes, but I realize a GPU of that size is a "whole nother critter". 

[smoothie]

BFL selling chips is a LAST-DITCH-EFFORT to bring in new money because they are about to go bust with their 60,000 preorder queue backlog.

Don't support their shady business practices which include deceiving and lying to customers.

[ecliptic]

   Design type: 100% Hand routed for performance density

Bullshit. They should change the supplier.

They must have found the shittiest design and verification engineers on the planet to get such low performance from a full custom 65nm asic.  Further, for a chip with such little logic on it their yields are crap.

My guess would be they used shitty engineers and global foundaries' standard cell library, the engineers didn't setup their simulations correctly and as such the cores fail under even the slightest real world heat.  This guess is additionally backed up by the high hardware error to accepted rates posted in screenshots by various Jalapeno recipients.   I would guess that the estimated hash rate on the pool side is much lower than the promised 5 gh/s.

Many people have speculated (Avalon themselves as well) that it's not actually a 65nm chip