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/topic as promised.

https://github.com/BitSyncom/avalon-ref

will be updated continuously within a next few days.

Much appreciated Yifu.  

We would also appreciate it if, due to the enormously time-sensitive nature of receiving Batch #2 or Batch #3 units, you gave us some kind of option to expedite shipping.  It's been >90 days since my order and I feel my brain literally melting each day that goes by.

TL;DR - Let me throw money at you to expedite shipping, or I could literally fly myself to Hong Kong and meet someone somewhere in the city to pick this up.  (Hopefully before ASICminer dominates the blockchain)

Thank you very much.

Do you know what packaging you will use for the chips themselves? (Tray, Tape & Reel, Cut Tape, etc)?

Also by chance will you include say, the solder paste stencil thickness & solder paste (probably Sn63Pb37) used?

Nice!

Much anticipated. Thanks

Agreed with this.

Really nice work!

can't find the bill of materials :/ which one is it?

EDIT: didn't read this xD

so how much longer?

Awesome stuff!  Looks like some folks are gonna stay up late for this.

+1

Patience grasshopper..

Awesome stuff.

Thank you.

I want to make myself water cooling elements for my (not yet arrived) Avalon.
I will reward whoever posts first the required measurements in a pdf or other open format with 0.5BTC.

edit: Never mind, I will do it myself.

Yes! Thank you!

Fantastic!  :)

very nice step, thanks Avalon Team!

WOOT!

Thank you so much Yifu! I was really looking forward to these specs. You never replied to the 1 PM I sent you, but I know you are a busy man :) See you at the conference.

Interesting that each ASIC has its own reset.

But is not connected. Tied high. I think this was for testing.

There is a capacitor on the pin. Obviously that's for delaying the power up of the chip.

Looks like an RC network with about 16 MS reset delay.

so would the sample chip be coming?

Thank you!

Let the hardware dev shitstorm commence!!!

Downloading altium viewer now  :(

Great. At least we know he's not dead.

Right on thanks!

geez.

thatta boy!

Can someone with enough knowledge tell me if a user that has avalon chips, can take this plans and let a company create a miner for him? Is it possible or is more needed?

Can it be done DIY, if you manage to get the parts?

And the software, firmware and so on is it freely available? I guess the miners that run with avalons would run with this miner too, right?

Today/this weekend, I'm going to investigate the building out of units based precisely on the reference design, and see if it'd be worth it to organize a group buy. This is hopefully assuming that Bitsyncom will be providing software. I haven't had a chance to look at the schematics in depth, but I didn't see a microcontroller, but rather an FPGA. Reverse-engineering what's happening inside it would probably prove to be a major pain.

I am currently working on pricing based on the layout. What's needed is the bom. The com protocol and software are needed to verify the design, and have been promised shortly.

Once all the info has been released I will have numbers for assembled clones.

An fpga sound expensive. The other miner developers dont need one. For example the klondike-project (see my signature). So im really wondering if the alternate design will be cheaper than the original one at the end. Interesting this all...

It's just for control and data pre-processing. It's not for hashing.

$24.27/pc in single quantities.
http://www.digikey.com/scripts/dksearch/dksus.dll?vendor=0&keywords=XC6SLX16-2FTG256C&stock=1

Thanks for the information...Now we have a lot of work for the weekend  ;D ;D ;D

When will you release some chips for developers ?!

Yes, the FPGA is an expensive part of the original Avalon design. Should the Klondike solution successfully eliminate the need for one, the miner cost will go down.


Sample chips will be sent out 4 weeks after batch purchase.

It looks like I may be working with a PCB assembler in California... How does one get in line for a "test" chip?

Find someone who purchased a batch who's willing to give you one of their samples.

Anyone have an idea how much sample chips will be send for a batch of 10.000 chips?

Speculating here... but my guess is a minimum of 32 and a maximum of 100, per 10K order.

should be enough to make a couple of board to test and tweak.. any way hope they will send out the chip in a couple of weeks

...there are some FPGA circuits, they should be programmed I think so.

+1

Weird, on the hash unit, the SS34 diode is missing from the schematic (PDF).

Maybe the uploaded data is not the latest revision? Also one screw-hole is missing on the hash unit.
Anyhow, nobody should use it without really understanding it - and this is not so difficult in this case. The know-how hardly lies in the PCB's in this case.

The only thing missing is the FPGA bitstream, right? (At least I couldn't find it.)

If Yifu Guo also provides the bitstream for the Spartan-6 chip, then we're done.  ;D

Well, it should be possible to read the bitstream from the flash chip on the control unit.
Someone with an Avalon just needs to do it ;-) (Maybe start a bounty?)

You'd think that if they want people to to make pcb/miners they'd release the bitstream and hdl source, right? Maybe it's just a matter of time. We are not overly anxious, right? Right? RIGHT?!?

So, after looking over the design and PCB and BOM of the ASIC, it seems that all that's needed to build a clone of Avalon s units is the FPGA firmware?  everything else seems to be online that's needed to the plans off to a PCB factory and get populated boards back.   I doubt at an individual level the costs of building a clone would be worth it, but if someone was building a large miner why wouldn't this be a better route to go then redesigning a whole new system

BKKcoins is working or will start working on an FPGA-less firmware for an FPGA-less design of his own. Seems the better route than simply cloning.

@BitSynCom,

When you get a chance can you provide some supply current estimates for the 3.3V and the AVCC 1.2V reference supplies per chip? I gather that AVCC drives the clock gen circuit and you have a separate supply to keep noise minimal on that line?

Thx!

It turns out that what Yifu released is a new revision of the hash unit PCB that does not need this diode. Most likely this is the revision that batch 2 and 3 will be built on.

Some resistors and inductors in Control Unit circuit are undefined. What does it mean "MB" an "NC"? And which value have:
FB1
FB2
FB3
FB4

R11
R13
R23
R24
R35
R4
R5
R8
R33
R34

+1

And what exactly 2SMX and 4SMX crystals need for Control Unit board? I found nothing about it model or even frequency..

/Edit because I should research before I post...

As mentioned below by fasmax, the FB parts are probably ferrite beads for EMI suppression. In doing some research there are also small surface mount inductors used for the same purpose. These are probably what the MB parts are. If you look closely at the pictures of the control unit you can see R8 and R11 which are "MB" parts on the schematic look like what chip inductors should look like.

If someone could post a better picture of the power section on the hashing module we could probably answer this question for sure.

As for values, lets get the BOM released!

-a[g

Would you mind uploading gerber and pick&place files?

Best regards

FB = Ferrite Bead.  Its an inductor that passes DC current and blocks AC (noise) it is low resistance at DC.
MB  I don't know what this stands for but it also looks like an inductor similar to FB but could have a more inductance and resistance.
The purpose is to provide a clean DC supply free of AC noise.
NC - Could that mean not connected ? Maybe someone could look and see if the NC parts are installed.

How is the BOM and comms protocol coming along for release?

We really need the BOM and communication protocol and power supply current estimates...

Some people have asked about the FPGA bitstream. It makes sense that the FPGA bitstream would be one of the last things they provide in order to work out any bugs. It could be changed very last minute.

On the other hand, it should be noted that they want to keep the bit stream to themselves. Do we know that they don’t mind completing with others using their reference board design? They might have just released the design as a form of documentation with no plan of allowing other to use it as a competitive product. Technically this is very easy. The Spartan 6 allows its bitstream to be encrypted - this makes it impossible to steal the bitstream.

Oh, and BTW, I know others are designing board which require no FPGA, but until we have communication protocol specifications we don’t know if that approach will work, or is even possible.

I don’t mean cry the sky is falling, but do we actually have a commitment on their intention with the ref board release? Personally, I’m planning on using the klondike design, but wanted to be clear that there are still risks.

Drew

You are right.
However, they are selling bare chips. So they have some incentive to support the DIY scene too.
Yes, it's two conflicting positions, from an economic view.
It is not conflicting if they have "the greater good of bitcoin" in mind.
And from all I have seen from Avalon, I am very sure exactly that is the point.

Oh, and kudos for not wasting your time playing in the bitcointalk sandbox, Yifu. I really mean it, I much prefer you to do real work instead!

Ente

Looks like BitSyncom pushed a new commit that has a datasheet with some comm protocol descriptions.

EDIT: For the lazy, the new document: https://github.com/BitSyncom/avalon-ref/blob/master/SPEC/A3256Q48-130507-V03-EN.pdf (https://github.com/BitSyncom/avalon-ref/blob/master/SPEC/A3256Q48-130507-V03-EN.pdf)

Also: https://github.com/BitSyncom/avalon-ref/blob/master/UNLICENSE (https://github.com/BitSyncom/avalon-ref/blob/master/UNLICENSE)

Lookin' good, team Avalon!

Thanks for the update BitSyncom!

One critical piece seems to be missing from the chip datasheet. How do you set the difficulty for the shares? Or is it fixed?

Also, is the HDL code for the FPGA coming?

-a[g

is their a way to set the fan speed at 100%?

This looks pretty impressive.  Wish I  knew what the hell I am looking at.  :o ???

You don't; all core mining algorithms designed to-date work to solve difficulty 1, as do these ASICs.  The controlling software is responsible for filtering out shares that don't meet the required difficulty.

I dont have any experience but wouldnt that mean there is hashpower going lost when it calculates things that cant be used and thrown away?

Nope; and besides, all mining algorithms work this way.

Now i remember... the difficulty was no var in hashing... it was only the border at which height a block could be found. When it was below no block was found.

Looking at point 10 it seems like the HDL code will be open source: http://store.avalon-asics.com/?page_id=9605

Thanks... help me out here to clarify my thinking:

At difficulty 1 the target will be: 0x00000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

Which is 32 leading zeros. This divides the 256-bit hash space in 2^32 segments. This means on average one out of every 2^32 hashes will be a valid share. So one Avalon chip at 256Mh/s will return a valid share once every 16 seconds.

-a[g

Yup, you've got it right.

Yes, except the Avalon is designed to do partial nonce ranges. So in practice you give each one a start nonce value and let it run some period suitable for the none to reach the value of the next range, after which it's wasting cycles. The controller needs to know when a range should be done and send more work. This divides the total nonce time by the number of Avalon in a chain.

I have a burning question,  I've sifted through the Github docs, but am having a hard time figuring out what cad software was used to create the pcbdoc and the Schdoc files. 
I'm assuming the BOM files were also generated by the same Cad program.  Anyone know?
Rassalas

Altium Designer. They do have a free viewer for Windows on their web site. No Linux sadly.

And the viewer is not free... gotta register.

iirc they made PDFs of the schematics, but i think they forgot and made it only of say, page #2 of a 2 page document, on some of them

the gerbers should be able to be viewable at least

Awesome release! Thanks!

  I don't think Altium is what was used.  We can't seem to load the SCHDOC nor the PCBDOC files with Altium designer.
If I'm wrong,  please do elaborate.
Thank you

I stand corrected.  We got them loaded.  looking nice.

What did you use? I tried KiCad, but it did not work... ???

Is the verilog/VHDL code for the FPGA also open source? Very
curious how they did the communication with the ASICs.

intron

Only binary version at this moment. Open source version of VHDL should be released later.
Also, check the git repository. Avalon datasheet is available there. Maybe you'll find what are you looking for in it.

From the readme file (https://github.com/BitSyncom/avalon-ref/blob/master/README.md):
disclaimer:
==========
current version of FPGA bitstream contains licensed parts we can not open source
 at the moment,
a licensed free version is being worked on that will be released in the future.

The datasheet is rather vague on some points. The HDL
would help very much. Or probing a running ASIC on a board...:)

intron

anyone got any news on the sample chips??

Sample chips will be big news when they start arriving.

Does anyone know an actual part number for the magnetic beads for each chip? The BOM says 60ohm@100MHz, but doesn't give a current rating.

I just registered for the altium viewer.
Has anyone made a CadSoft EAGLE version of these documents?

Yes .. i read datasheet and I couldn't find, how the report n, p timing is done.
Friend of mine has sample chip, he can send config and sample data into chip, it calculates golden nonce, but output has some strange timing. It look like it's derived of external oscillator frequency, but how?