With lots and lots of $9 JTAG cables.  Inspector, do you need some kind of jtag hub? I mean, on one side we have the jtag connector, but on the other side? spiccioli USB typically. Back in the old days, they used to hook up JTAG controllers to the parallel printer port... <wanders off into the distance, muttering about the old days when JTAG ports were still hooked up to LPT1: and a gallon of gasoline cost less than a buck> |
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Motherboard designers are not dumb. If it's fused with a 1.5 Amp fuse, the fuse will blow before the trace burns through or the motherboard incinerates. That's precisely why the fuse is there in the first place.
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On a typical motherboard, a USB port is fused with a 1.5 Amp fuse.
Plenty of headroom.
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With lots and lots of $9 JTAG cables. |
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AFAIK, there are restrictions shipping to Cuba, North Korea, Iran and maybe one or two others.
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"cafe babe" - wow.
Much better than
"dead beef", I think.
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does anyone run sigles sitting on their side (on a wire rack) I was wondergin if this woud have a negative effect on cooling or operation
I run them sitting on their pretty FACE. The FACE being the only surface which has neither vents nor connectors. Makes it kind of hard to see the "throttling LED", though. One can still see the throttling LED when peeking through the vents. |
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Exception in thread "main" java.io.IOException: java.lang.RuntimeException: Error sending data, ztex error -22
That's an error from ztex's code. Any ideas?
Try powering the board off for 5 seconds and powering it back on. Also, make sure his miner isn't running in the background. Doesn't help. This issue is 100% reproducible for me. |
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I followed the instructions on the tricone-mining site, and this is what happened:
* it means your power supply is sagging. *
* *
******************************************************************
[ztex:0 ] programming FPGA
[ztex:0 ] done programming FPGA
Exception in thread "main" java.io.IOException: java.lang.RuntimeException: Error sending data, ztex error -22
at com.triconemining.board.Ztex$ZtexChip.flush(Ztex.java:207)
at com.triconemining.board.Ztex$ZtexChip.scan(Ztex.java:167)
at com.triconemining.board.MiningChip.read(MiningChip.java:48)
at com.triconemining.bitcoin.miner.Miner.checkMagicNumber(Miner.java:166)
at com.triconemining.bitcoin.miner.Miner.<init>(Miner.java:34)
at com.triconemining.bitcoin.miner.Main$1.<init>(Main.java:359)
at com.triconemining.bitcoin.miner.Main.main(Main.java:359)
Caused by: java.lang.RuntimeException: Error sending data, ztex error -22
at com.triconemining.board.Ztex$ZtexChip.flush(Ztex.java:193)
... 6 more
Any ideas?
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I'm pretty sure I saw a video online of a HP exec demoing their hardware testing facility. They were repeatedly zapping their laptops with a 75,000V gun.
I find that very hard to believe. I tested some hardware myself and the existing standards demand 10000 V or 12000 V, I forget which one. 10000 V *roughly* corresponds to a 10 mm long spark. 75000 V would thus correspond to about 3 inches. That means, even light pipes of 1 inch length would be insufficient for preventing a spark from entering the circuit via a simple indicator LED. For military equipment, maybe they test to more then 10 KV. For consumer equipment, no way. |
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Okay, I'm gonna pull the trigger on this thing. I have posted tml-0.9.jar. Only 222MH/s right now, but it's a start, and this way I can start to get feedback and independent confirmation. Don't expect 222MH/s unless you have a really good cooling setup. No commissions for at least the next week. There will be another small speed bump in the morning or early afternoon tomorrow when the next build finishes; once that's out I'll make a more formal announcement. No press releases this time, though… I've depleted all $89 of my press budget. The jar file also includes the final version of the board developer API. Would you be so nice and tell me whether this JTAG software you are using supports the original Xilinx JTAG tools? Because that's all I have. |
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How heavy are they? 10-20 pounds? Or more?
+1 Gigavps should know - he just shipped one of them back to BFL. |
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IMHO, Actel has technologically fallen behind the two FPGA market leaders, and Actel's devices, being EEPROM-based, are also more expensive than comparable products from Xilinx and Altera, thus: Nothing to see here, move along.
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Hrm.
So, I have a bitstream that will run error-free on the ztex board at 170mhz as long as I only use one of the three rings. I can also run any one ring at 170mhz and the other two really slow (like 50mhz slow). But if I use all three rings at full speed, I get errors all the way down to some pretty embarrassingly-poor hash rates. I experienced a similar phenomenon on my own boards, but it wasn't nearly this severe and the optimal clock frequencies were still giving me 245+MH/s on my SG-2 boards (ztex uses faster SG-3 chips).
I'll be doing some more experiments on the clock-rate/error relationship this evening, but the important questions require a new build in order to answer, and that's going to take 24-48 hours (sorry, folks). Still lots of tricks up my sleeve, but they take (build) time.
Bitfury experienced a similar thing. It's probably ground bounce INTERNALLY to the FPGA. Or something like that. Xilinx never designed their FPGAs in such a way that 95% of all flip-flops could switch at the same time. They just didn't. But that's what a miner does. |
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So I wonder how easily this could be reconfigured into a "fuck rainbow tables, crack passwords in realtime" type appliance. 1 bitcoin terahash per second is 2 regular SHA256 terahashes per second, which is a lot...
I'm going to guess not useful at all, unless the passwords happen to be hashed with SHA2. twice. |
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Also, I seem to recall there's code out there to emulate the Altera USB Blaster JTAG adapter using a Cypress FX2 like the one on the Ztex board, e.g. http://fpga4u.epfl.ch/wiki/FX2. No idea how practical it'd be to port it though. On ZTEX boards, the FPGA's JTAG signals are not even connected to the Cypress FX2 microcontroller. |
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Is this already Eldentyrell's bitstream???
No, it is running ztex_ufm1_15y1 bitstream from ZtexBTCMiner-120417. I was asking, because in a different thread, EldenTyrell wrote: "the first Bitstream I'll post will be a 230 MH/s design" So, if the standard Ztex Bitstream already achieves 230 MH/s, what's the f***cking point of bothering with ET's clever scheme of only accepting encrypted start vectors, and then decrypting them in his Bitstream, and only generating encrypted golden nonces? <confused> |
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001-0: ztex_ufm1_15y1-04A36DF26A-1: f=232.00MHz, errorRate=0.23%, maxErrorRate=1.83%, hashRate=231.5MH/s, submitted 11 new nonces, luckFactor=0.90
001-0: ztex_ufm1_15y1-04A36DF26A-2: f=232.00MHz, errorRate=0.00%, maxErrorRate=0.00%, hashRate=232.0MH/s, submitted 15 new nonces, luckFactor=1.15
001-0: ztex_ufm1_15y1-04A36DF26A-3: f=232.00MHz, errorRate=0.21%, maxErrorRate=1.87%, hashRate=231.5MH/s, submitted 18 new nonces, luckFactor=0.94
001-0: ztex_ufm1_15y1-04A36DF26A-4: f=228.00MHz, errorRate=0.00%, maxErrorRate=0.59%, hashRate=228.0MH/s, submitted 17 new nonces, luckFactor=0.94
Sweet! Is this already Eldentyrell's bitstream??? |
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Exactly my thoughts.
Automobiles should never have been allowed, because their success caused the demise of livery stables, horse whip manufacturers and horse buggy manufacturers.
Or maybe automobiles should have be allowed after all, but the ordinance that a man with a warning bell walks in front of them should never have been rescinded.
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Are the Xilinx-brand JTAG cables supported? None? All? Some? If the latter: Which ones? I have no experience with urjtag, even though (or maybe because) I sold JTAG hardware myself about a decade ago. |
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