Since this refers to my message that wasn't clear: Xilinx bitstream format WAS at one time available to Xilinx EDA software partners, possibly under NDA, possibly under some different sort of legal and financial protection. I no longer consult for that EDA vendor and I have no relevant knowledge regarding current products. I only remain friends with people who continue to maintain and upgrade the EDA software applications that I co-authored years ago. It seems plausible that companies like Synopsys get access to the bitstream format, possible for a fee, but less plausible that any Tom, Dick and Harry could get access to it. |
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In SHA-256 round expander kills routing, as taking that w[0], w[1] and w[9] requires a lot of routing, because you basically pulling data from N rounds behind...
Oh yeah, I totally forgot about that. Now you got me almost convinced that such a sea of small blocks is the better way to do it. Live and learn... |
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Explain your marketing:
BFL couldn't sell enough units at $30k so they came up with one at $15k, and you jump in straight with $90k?
As explained on their website, they were expecting even higher hash rates. The ISE tool even led them to believe higher hash rates are achievable, but in practice the error rate was too high and they had to downclock to 240 MHz. Wow, I can't believe I just said "downclock to 240 MHz". |
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...
From a technical perspective, I beg to disagree.
There's a thermal resistance RT1 from the die to the heat spreader, and a thermal resistance RT2 from the heat spreader to the cooler. While RT1 cannot be changed, it is a good thing to minimize RT2. One way of minimizing RT2 is by removing the heat from the whole area of the heat spreader.
So ... that edge is OK (cool) to touch with your finger right?  Coz if it wasn't, none of this discussion that saying it doesn't matter would make any sense to me ... Exactly my point, Kano. Of course, the ledge that is not covered by BFL's heat sink is NOT cool to the touch. |
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This is most likely due to the Spartan6's awful long distance routing fabric,
This isn't Spartan's fault. This is a property of any modern FPGA: most of the delay and energy loss occurs in the routing fabric. So the easiest way to speed up the design is to minimize the demand on routing resources. I was always perplexed why everyone here was focusing on unrolling the combinatorial logic. After gaining some experience with the currently available EDA tool suites for FPGA it became obvious: they make the place and route of repetitive designs very difficult. The "sea of tight hashers" approach will probably be also beneficial for the future ASIC designs, although not by such a wide margin. Does anyone know if bitfury's design stores the SHA-256 constants in BRAMs or has them spread over through the SLICEs? In a completely unrolled design, there are no long lines. The start vector is fed in on the left side, then the calculations percolate down to the right, and at the right a "matching" circuit determines if a "golden nonce" was found. There is no feedback from the right side to the left side. Thus, while I do think that Bitfury's approach is EASIER (as one only has to worry about a few hundred wires and their associated delays, and not tens of thousands), I fail to see why it is inherently faster. I don't think it is inherently faster. Maybe the Xilinx router goofs up wires that would be short and local and sends them the long way like a crooked cab driver an out-of-town tourist. But, to reiterate, a fully unrolled miner does not involve a feedback from the right side to the left side. |
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My 2 cents:
The pricing is pretty much OK, but the AES key programming could turn into a logistical nightmare.
In a few days, EldenTyrell will reveal his offer and if it is competitively priced, but does not involve sending boards back and
forth for AES key implantation, it'll probably be the offer I'll pursue.
Well - sending boards back and forth is bad case, and it will not work that way. Better case to program it in place where they are assembled. But that requires high level of trust to one who is doing such programming. Also it is cheaper to assemble in higher volumes. So if there will be 1, 2 or 3 points of PCB assembly with nice flows of chips - it is not problem to get trusted person, who will turn board on, program AES and done. I am ready to solve it, so it would be without any delay. But not for 20 points of assembly (soldering of PCB, not building complete product) with 10 chips per month each. Anyway - to get good prices you have to make volumes, this is why we started with racks, and not with small units - it was much cheaper that way. EDITED: Or - how else could it be protected ? Because selling it for $20 is like uploading it to ftp. Say you will not pirate it, but one of 100 users would certainly do, and they'll even think that they did it right way. EDITED: Or another possibility was offered - that if chips are supplied to different board vendors using same channel, then we could program chips at some point during their initial delivery. Probably this could be best option for smaller purchases, but it depends. I am prototyping my own design as we speak, and thinking of having 100 boards (or 127 boards, because the assembly quote was for 127 - don't ask) assembled in China, at a relatively unknown assembly house, and then shipped to me. I do not know whether this unknown assembly house would have the technical know-how to burn in an AES key into the FPGAs, in fact right now I have no plans to have a JTAG connector populated. And I do not know whether this unknown-to-you assembly house in the middle of China (literally) would have your "trust". But, since I'm in NorCal and you seem to be in Los Angeles, maybe I can just drive down to you one weekend, you program in your AES key into all 100 (or 127) boards, and I hand over a check for 2 grand (or 2.5 grand). Or cash, if desired. Maybe we can work something out. Right now, the current revision of my board has a relatively weak DC-DC converter chip on it (which I actually bought from someone on this forum, but I don't blame him - who could have foreseen bitstreams so fast) and I need to redesign the DC-DC converter to a 12 amp one. While I redesign it, could you be so kind and disclose the PINOUT that you have, i.e. the .ucf file. In other words, I'm redesigning the board ANYWAY, might as well redesign it to conform to your exact pinout... |
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My 2 cents:
The pricing is pretty much OK, but the AES key programming could turn into a logistical nightmare.
In a few days, EldenTyrell will reveal his offer and if it is competitively priced, but does not involve sending boards back and
forth for AES key implantation, it'll probably be the offer I'll pursue.
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Has anyone else noticed how the heatpipe cooler on the rev3 doesn't really cover the second FPGA? It is short by about 5cm. The center of the chip is covered but one whole side is left open.
I noticed this also. If this heatpipe is really custom made the job wasn't done good. I'm thinking about putting a metal plate between the FPGA's and the heatpipe. This metal plate should cover the full area of both FPGA's and transfer it to the heatpipe. Maybe this could improve the cooling which is obviously mainly limited by the only parted covered FPGA. Has someone already done this? Adding any additional substance will only increase thermal resistance and makes cooling less efficient. The aluminium plate which the heatsink sits on, is a by itself a heat-spreader directly attached to the die inside. Regards, BF Labs Inc. I would agree here, don't add anything extra or your temps will just go up. The heatsink itself could be better for sure, the aluminum part could be solid copper for start; and I noticed it is slightly short as well, however the copper pipes seem to touch the surface of the chip where the aluminum part cuts off, so that's something I suppose. Again... to clarify... (trying to save unnecessary efforts among users), the chip itself is smaller than the aluminum heat spreader you see. There is no purpose in trying to extend the heatsink out to the edge of the heat spreader because there is no heat being generated under the edge... There is only air there. See picture above for visual reference. From a technical perspective, I beg to disagree. There's a thermal resistance RT1 from the die to the heat spreader, and a thermal resistance RT2 from the heat spreader to the cooler. While RT1 cannot be changed, it is a good thing to minimize RT2. One way of minimizing RT2 is by removing the heat from the whole area of the heat spreader. |
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Or am I missing the point here?
Could it be related to the fact that a Bitcoin hash only needs 61 rounds instead of 64? No. Completely unrelated. A guy or gal named Valery just responded to a personal email of mine with the clarification that they are indeed talking about 8 x 30 slices, the same number a count on their screen shot comes up with. In other words, 8 x 32 was a typo, which they have corrected on their website by now. |
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On their website, they state: Then after choosing serial round design it was very challenging to fit it exactly into 240 slices (8 x 32 area). As you see in snapshot image on the left, magenta color shows exactly two SHA256 rounds location. These double-SHA256 with round and round expanders and additional control logic fits into 240 slices. This took another month of development. Fitting in 240 slices was important to obtain good fill of XC6SLX150 right part.I hate to break the news, but 8 x 32 is not 240. It is 256. At least, where I grew up.  So, what did they really do? Fit two rounds of SHA-256 into 240 slices, including control logic? I find that hard to believe. Or fit two rounds of SHA-256 into 256 slices - I find that slightly easier to believe, but it still would be a major achievement. i believe because we did just exactly the same. 2X 64cycle SHA256 core in 8X32 area, include control logic, timing report is much over 300MHz. the coding work is easy(maybe less than 50 lines.) but write the UCF files used month of time, and still have some small bugs now.  My point was, that 8 x 32 is not 240. It is 256. If you can fit this in only 240 slices, then maybe 16 x 15 is a better geometry, since 16 x 15 really is 240. Or am I missing the point here? |
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On their website, they state: Then after choosing serial round design it was very challenging to fit it exactly into 240 slices (8 x 32 area). As you see in snapshot image on the left, magenta color shows exactly two SHA256 rounds location. These double-SHA256 with round and round expanders and additional control logic fits into 240 slices. This took another month of development. Fitting in 240 slices was important to obtain good fill of XC6SLX150 right part.I hate to break the news, but 8 x 32 is not 240. It is 256. At least, where I grew up. So, what did they really do? Fit two rounds of SHA-256 into 240 slices, including control logic? I find that hard to believe. Or fit two rounds of SHA-256 into 256 slices - I find that slightly easier to believe, but it still would be a major achievement. |
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A veterinarian uses this kind of oil to try to clear a colic (colon blockage) in a horse. I saw a vet do that. Thus, in other words, you could use it as a laxative, if you wanted.  |
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Wow - someone has out-eldentyrelled eldentyrell...
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There are 2 or 3 counties in rural Washington where there is an abundance of hydroelectric power, but not enough high-tension lines to get the power to, say, Seattle. Thus, they almost (but not quite) give it away.
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The feedback on Newegg doesn't exactly sound confidence-inspiring... |
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I wonder if existing Spartan6 boards people have will require hardware changes for this firmware, like power related circuitry
He has already said that the ZTEX boards, including the latest and greatest 1.15y, will draw more power using his 1 1/2 miners (or 3 half-miners) compared to the original 210 MH/s ZTEX bitstream, and since they all have a 8 Amp DC/DC converter, the headroom is small. Just HOW small, I don't know. |
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Because they haven't been released yet. They do have in-house prototypes, but still a lot of validation ahead of them prior to release.
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They have access to Intel 22 nm foundries. The deal probably works somewhat like this: Achronix has a minimum guaranteed number of monthly wafers, and an option to run more wafers in case Intel does not need the full fab capacity. For both parties, this is a win-win situation.
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So the Single is an FPGA so can be reused for a similar task, but mini-rig is a proper ASIC so application specific, no reuse possible ?
It's my best guess - don't take it for a fact just yet. |
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I think this time it is a structured ASIC.
They handed over some 300 grand to Altera to have a HardCopy chip (structured ASIC) made.
Naturally, without the parasitic capacitance of all the interconnect transistors, the HardCopy is faster and more power efficient.
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