The math is:
   BTU/hr=Watts x 3.4129
   1 Tonne=12,000 BTU/hr

So for 12kw load you are producing 40954.8 BTU/hr or 3.4129 Tonne of heat to be moved.

Interesting. Too bad the seller didn't provide more info in the input connections. I am guessing that it uses either an external milli-ohm high current sense resistor or more likely a current transformer. The seller should tell us that and if said parts are supplied...

As for exposed connections: Of course they are. It is a panel meter made to be mounted in a control box...
Being able to monitor 220v is a plus because a) Many countries use that as the normal mains voltage and b) most high power loads (eg PSU's) run better on a high line.

Keep in mind that computer PSU's are made to supply 12v or slightly more. Very few can be throttled lower. The nature of delivering power over wire means that by design a (computer) PSU should only need to compensate for voltage drops over the wires. As a result there is little to no downward adjustment possible without modifying the feedback circuit.

Thee is no failsafe in the miner for that. What you can expect is very short PSU life, increased HW errors and dropping ASICS (x)'s possibly entire board, requiring a hard reboot (cycling the power). In short - don't do it. For reference, at stock speed my s5's draw 630w from the wall with Gold PSU's.

heh heh. Long enough to see that yes, everything old is New again. First vacuum tubes - high impedance & voltage controlled, then transistors using low impedance/voltage/higher current and now with all the various members of the FET family back to voltage vs current, Analog > digital and now > mixed level digital (more functional states per-gate but with higher power needs as well) which to me is headed back to quasi analog computers....

I'll check out the thread.

I'll also add that ja the ASIC's are key to what can be processed but as the poster child of failed board design and manufacturing shows (Bitmine.ch), all the support circuitry and attention to board layout/physical construction is just as critical to pay attention to

  Why thank ye for the plug . Coming from you I take that as rather high praise
Since we are in disclaimer mode here: I too have never laid out silicon. I do not know or care to know the actual hardwired logic pathways in mining ASIC's. I do know more than a thing or 2 about high speed circuitry and the care/feeding thereof... My first experience with high-speed circuit layout originally comes from working with/building microwave coms gear in the early 1970's. Thing is, with the logic switching speeds ASIC's use all the same rules apply regarding local power decoupling and signal integrity vs the path routing. It is not only clock speed that gets you. More problematic is the rise/fall times of the signals inducing high levels of very localized odd-harmonics into the power plane and data signals.

Anywho, for the past 39 years my biz has been designing/building from framework to the control boards equipment used in some rather critical steps in chip fab processes. We build bleeding edge tech that makes making bleeding edge chips possible. That in turn is where my contacts with the semiconductor bix comes from. Natural curiosity and the need to know about all steps and I mean all involved is what keeps me current on what node-sizes the various major foundries can produce;) As for my blasting pre-packaged IP blocks a foundry or chip design house can provide, it is a common sense  item any decent chip designer should follow if the goal is Best-in-Class. Far more risky yes because simulate all you want, until it is physically produced there is no third-party assurance (someone else to blame) that each function block actually does what it should.

If you want a 'safe' moderate performance  first run chip as proof of concept, then use pre-packaged IP function blocks. They are proven to work and just need to be placed best as possible in the die and linked together anyway ya can. *That* is along the line of what that chip design site mentioned earlier on sounds like they do. At the more mature 22nm and higher nodes foundries can often provide short-runs by using 'spare' space on wafers to make more money per-wafer on what is often razor-thin margins from generic chips made on the same wafers. I rather doubt that 'low cost' option is yet available at 16/14nm. Scrap rate is still too high

As for hashing ASIC's themselves I highly recommend reading through the A1 chip dev thread starting here. https://bitcointalk.org/index.php?topic=294235.360. I dived in there due to my ordering on of the ill-fated AMT/Bitmine.ch A1 based miners in Feb. 2014. It is a good read on the trial and tribulations of giving birth to a new miner design. Also points to, hell, screams where Bitmine.ch went so very wrong with their boards...

Enough of the mutual admiration club and back to the Topic. To the OP I say, if you think you have a core team that can do it then go for it. The mining community needs hardware choices. Just fully research what is going to be involved and round up (fully informed of the risks) investors. Again, I highly recommend that A1 dev thread for insite on what to expect.

I guess practice makes perfect

Any correlation to them changing to using string topology vs multiple buck regulators with chips fed from a common power plane (in banks)? I sorta wonder how much interaction with the buck switching freq vs core freq they were seeing...

Query: are Bitmains chips uni-planar or a 3d stack like the A1's were? In an ultimate case of using pre-packaged IP InnoSilicon as I recall had the cores, then a memory layer topped by an SPI coms layer. Each separate silicon tied together with ISV's and wire bonds.

^^ +1 !
Throw in the fact that design rules for 16/14nm nodes is still a Work-in-Progress because the mfg processes are as well and you see why after years of promises those nodes are just now becoming available to companies other than IBM, Intel, AMD, and Samsung et al.

thanks for the correction om chip #'s  was an off the top of me head dismembering of them

As for the freq/core voltage, probably has to do with how well the data eye can be kept open over the chips internal signal paths between the different parts (coms, memory, cores). That bit is where custom routing helps immensely because you can layout the I/O of each block to provide the shortest paths to the other function blocks. Shorter path = lower capacitance to charge/discharge = faster speeds at same or hopefully also lower power consumption.

Dinna know that Bitmain gained enough to actually use fewer cores per chip and still get the results they got.

Well sounds like a good start. The chip designer is a person who will be critical as I suspect that design site will be pushing you to use pre-packaged IP function blocks that are just linked together to create the desired chip functions. While that can work using pre-packaged IP also means that you will be making the signal connection paths based on what the IP block gives you - that in turn means non-optimal performance. Prime example of the difference custom routing gives you is Bitmains '1384 vs their '1385 chips. Same circuitry but by using custom routing in the '1385 function blocks themselves Bitmain drastically improved the power/hashing performance.

I thought that might be your confusion. Glad to help clear that point.
Your only source for new chips is to contact the foundries customers, eg. InnoSilicon, Bitmain, BitFury, etc. They are the ones to talk to about chip sales.

What chip from TSMC? Do you have any credentials or at least contacts in the semi business so they will even talk to you?

TSMC does not 'make chips' of their own design. They are a foundry that makes chips for other companies using those companies designs. Now if you have a chip design ready for simulation and perhaps ready for making test masks along with around 1million dollars to get their interest, then you are all set.

Will do. So far been 7hrs since I directly contacted Bitmain and got an auto reply saying they got the msg. My initial contact to Zendesk explaining the tests I did was answered within an hour. They said time to contact Bitmain. fun fun fun

Even though just 1 bad board out of 11 s7 ain't bad, if BTC goes up a bit more I prolly should get a b9 just for spares...

In a way, this points to the biggest disadvantage to high TH/s per miner such as the s7 or BitFury's supposed 20TH/s rig vs things like a pharm of Pod's or stick miners. Sure takes up more space but for Home miners or small to moderate sized miners like me (and 1 year ago I never ever would have called ~70TH/s total 'moderate') if a miner goes down you don't immediately drop 4.7 THs or more of hashing.

Hmm. UPS kept reporting it was stuck in St. Louis due to weather.
Anywho - Merry late Xmas! I see I forgot the 4 s1 boards from the 2 s1>s3 miners. If ya want them for buck parts I'll send them with the hosted miners next week. One of the new s7's that is replacing them here has one blade DOA so am seeing if Bitmain will let me send just the 1 dead board in RMA...

Once the snow from the storms in your area is cleared so UPS can deliver you will have 3 s5's in the load of donations I sent ya
-Cheers!

Ja. If they themselves are not interested in getting into the 'selling shovels to the (gold) miners' business then most definitely they should either just non-exclusively partner with an assembler/seller of miners or release a reference design and sell chips to whomever wants whatever MOQ that is enough for them to bother with.

I'm just glad that Bitfury is doing a proper announcement of these chips, making it known that they have a viable chip and it is in testing. Period. No taking pre-orders from the general public on what might or might not work as opposed to taking the BFL (Monarch)/Bitmine.ch (A1) route of grabbing all the cash they can before even having engineering samples.

I'd think that it is a safe bet Bitmain has something similar in the works but being Bitmain they are quiet about it so current chip/miner sales are not impacted.

As for reverse engineering... The chips? Decapping them to see the innards of it would be of no help to Bitmain/Avalon/whoever. While block and signal path layout is critical to max performance (eg Bitmain's 'optimized' chips in the s7) , seeing what Bitfury did is a waste of time. Chip designers know how to do it right, the problem usually is that project managers rarely take that route because it costs (and risks) $$$ vs using pre-packaged IP blocks provided by the chip foundries.

As has always been the case the biggest hurdles to 16/14nm gate-size chips of any sort is the process itself. Only late last year did TSMC take their 16nm chip production from limited boutique chips & engineering sample runs to full open production. Once the few foundries that are capable of running 16/14nm chips have the process nailed down enough to lower the scrap rate you will see everyone and their brother jumping on the bandwagon.

Stock picks based on past performance have nothing to do with random chance. In stocks there are Humans 'with a Plan' guiding performance vs random events. That Human influence throws a huge bias in a stocks performance. Yes random outside events will have an effect on performance but nowhere as near as much as the Human guidance does which will deliberately work to offset serious random disturbances..

Running with the Bitmain 1600w PSU my s7b8's, as reported by my UPS's are all pulling 1,220-1,255w from the AC plug. Running stock clock speed all have been pretty rock solid at a daily average of 4.7-4.9TH/s sometimes hitting as high as 5.8THs (and occasional lows of 3.8TH/s) over a 10min period as reported by my pool.