Bitfury: "16nm... sales to public start shortly"

[sidehack]

Less than 10% operating correctly? So, about 820 cores instead of 8200? How's that pass inspection, or am I missing something? Admittedly I know nothing about the logic implementation of hash cores.

[1713906426]

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[2112]

Less than 10% operating correctly? So, about 820 cores instead of 8200? How's that pass inspection, or am I missing something? Admittedly I know nothing about the logic implementation of hash cores.

It will pass inspection at a lower grade and will be sold for a lower price. But its ratio of hash speed per power used will still be better than the competition.

I am making one assumption that somebody's at Bitfury has at least one brain cell working and will include circuitry to disable clock distribution to non-working hashing engines. If they have more than two working brain cells together they will include a way to fuse-out power to the non-working engines and there won't be even leakage.

The other thing increasing yield in mining chips is that they are 100% self-love, they don't have to meet any external timing constrains. If the defect is wafer-global, like all transistors have 1/3 of the normal Fmax, the chip is still competitive in GH/J and can be sold at a different price point.

The biggest yield differentiator is that SHA-256 is self-testing and requires exactly zero functional testing circuitry. The regular chips made for big-name customers most definitely require that at least the JTAG chain is operational on the whole surface of the chip, even if many functional units are defective and will be disabled when sold.

The NAND flash folks have this down to art. 90% chip not working? Sell it as a 10% capacity chip! Chip fails after 10 erases? Sell it to promotional merchandise vendors or as a one-time-programmable!

Bitfury folks seem to be rather intelligent. Their first chip included some analog self-test circuitry (ring oscillator?) that allowed for testing of the maximum speed that the chip wants to work (at particular temperature and supply voltage). It may not have worked as intended, but shows the grasp of technology.

The opposite can be said of Spoondoolies. They wasted chip estate for including some POST (power-on self test) circuitry. And then their software guy had to write code that re-enabled disabled engines which were failing only when cold and worked fine hot.

Edit: Remember the first Bitfury chip? They were 100% defective if one would try to apply traditional test methodologies. But somebody from Poland within first few days reverse-engineered the "defect" which turned out to be some sort of permutation of signals like (15-0) -> (1-16). They added appropriate compensating permutation in the driver and sold all of them.

[HyperMega]

<snip>
This would result in about 3200 good dies per wafer. Right?

70000 mm² per 300 mm wafer and assuming 90% yield a single die size would be about 20 mm² (4.5mm x 4.5mm), which would fit to the package size.
<snip>

90% yield?  
That is WAAAAAY off base. That yield is common for higher nodes like 28nm on up but currently 16/14nm production yields are around 40% good dies and lower. They only began to hit 40% late last year...

Now the foundries are of course trying to get better but the processes are still under development. Biggest issue is the EUV light source used for the photo lithography. That monstrosity is still pretty hairy to run and is in no way capable of running 24x7. Is more like 8-20hrs followed by around 6 hrs to a full day of cleaning/realignment/process verification before starting another run of chips.

Sorry, but the foundries still managed to get 14/16nm working without EUV. Currently they are thinking that they need EUV starting with 5nm.

Normally SRAM is killing the yield of new technologies, but there is no SRAM in a Bitcoin Mining ASIC. In general these mining ASICs are very resilient and can also live with some faults. So I#m pretty sure, that one can achieve allready very high yields with a robust design style.

[HyperMega]

If going by area, wouldn't shrinking from 28nm to 16nm be a factor of 3 decrease?

No, 16nm use the 20nm BEOL (metal stack), which means there is almost no shrink from 20nm to 16nm.
And there is a classical shrink of a factor of 2 from 28nm to 20nm, like moore's law told us for many years now.

[HyperMega]

For general info on the light source being used and its current status https://www.gigaphoton.com/en/news/3770 Note the date of the release.
They mention hitting a 24hr benchmark but that was an extended test run on a prototype and do not mention that it was test run only. That time between rebuild has not yet hit the foundries floors. btw: Gigaphoton and 1 other vendor makes the system which incorporates modules from other suppliers. Both use the same laser source and basic process to generate the EUV from their interaction with tin droplets.

One good sign of the various foundries confidence that the current tech used to generate EUV will be viable is that the sole supplier of the laser system used in it spent 70M euro's last June on an expansion to dedicated to make the lasers needed. http://optics.org/news/6/6/31. Has a good is basic description of how the EUV light is generated as well.

For info on TSMC's 16nm pr http://www.tsmc.com/english/dedicatedFoundry/technology/16nm.htm
Main consumers of TSMC's production http://www.tsmc.com/english/dedicatedFoundry/technology/application_specific_platform_solutions.htm Note that boutique ASIC's (eg for miners) don't even make the list unless maybe they fall under Power IC.

From 6mo ago, a hint at one of the players that have been footing the bill to reach 16/14nm chips http://wccftech.com/tsmc-begins-volume-production-16nm-finfet-nvidia-pascal-gp100-gpu/ It is only due to folks like them that targeted mid-volume high-end commercial/consumer use pricing has become available. Also one guess what fruity company has bought up almost all the current 16nm production capability of TSMC leaving far less available for miners (so far).

One other bright light at the end of the tunnel: keep in mind what foundries like TSMC, GloFo, and Samsung (Intel and IBM don't count here) consider when talking production volumes. Those are the ONLY foundries able to produce high volumes of 16/14nm chips. Period. Talk several hundred million to around 3/4 billion or more chips per month and you have their rapt attention. They won't even talk to you about 'boutique'' runs of only a million or so per month. I can't see the combined demand from BitFury and Bitmain being more than around a few hundred million chips/mo at best once things are proven out. But, with the processes getting better, miner ASIC's are able to tag along in many of the production steps and that translates into a lot of available custom chips space per step. Hopefully by now BitFury is up to full wafer status (with the attendant ~40% yield per-wafer). With Bitmain probably not far but silently behind???

All that said and done, it will certainly be interesting to see how BitFury's chip comes out!

FYI

http://www.extremetech.com/extreme/210427-tsmc-confirms-volume-shipments-of-16nm-pushes-euv-back-to-the-5nm-node

[NotFuzzyWarm]

90% yield?  
That is WAAAAAY off base. That yield is common for higher nodes like 28nm on up but currently 16/14nm production yields are around 40% good dies and lower. They only began to hit 40% late last year...

Now the foundries are of course trying to get better but the processes are still under development. Biggest issue is the EUV light source used for the photo lithography. That monstrosity is still pretty hairy to run and is in no way capable of running 24x7. Is more like 8-20hrs followed by around 6 hrs to a full day of cleaning/realignment/process verification before starting another run of chips.

90% is a lowball estimate. The actual yield will be higher. The mining chips are so repetitive that they are commercially valuable even if less than 10% of it is operating correctly. It is the same story as with NAND flash memories.

The 40% yield refers to number of good chips per wafer - not cores per chip. As to what is a good chip, it one that meets spec. Preferably with 100% cores active @ stated speed. From there they will start stepping down the grade hopefully mainly by speed capability instead of by dead cores.

[sidehack]

If going by area, wouldn't shrinking from 28nm to 16nm be a factor of 3 decrease?

No, 16nm use the 20nm BEOL (metal stack), which means there is almost no shrink from 20nm to 16nm.
And there is a classical shrink of a factor of 2 from 28nm to 20nm, like moore's law told us for many years now.

Right, I forgot about that part. Thanks.

[NotFuzzyWarm]

<snip>
This would result in about 3200 good dies per wafer. Right?

70000 mm² per 300 mm wafer and assuming 90% yield a single die size would be about 20 mm² (4.5mm x 4.5mm), which would fit to the package size.
<snip>

90% yield?  
That is WAAAAAY off base. That yield is common for higher nodes like 28nm on up but currently 16/14nm production yields are around 40% good dies and lower. They only began to hit 40% late last year...

Now the foundries are of course trying to get better but the processes are still under development. Biggest issue is the EUV light source used for the photo lithography. That monstrosity is still pretty hairy to run and is in no way capable of running 24x7. Is more like 8-20hrs followed by around 6 hrs to a full day of cleaning/realignment/process verification before starting another run of chips.

Sorry, but the foundries still managed to get 14/16nm working without EUV. Currently they are thinking that they need EUV starting with 5nm.

Normally SRAM is killing the yield of new technologies, but there is no SRAM in a Bitcoin Mining ASIC. In general these mining ASICs are very resilient and can also live with some faults. So I#m pretty sure, that one can achieve allready very high yields with a robust design style.

No, the foundries *are* using EUV right now despite the problems. I've worked with the companies involved.

Yes until EUV became better last year they pushed double patterning with conventional light sources far beyond what was thought possible but in no way did it work well enough for what the semi biz calls high volume production. TSMC and GloFo both use 13.8nm light sources while Samsung uses 9.5nm light (which is why they are producing actual 14nm junction chips vs 16nm). The talk of pushing back to the 7 and 5nm nodes was referring to that EUV may be able to work there as well instead of hitting a wall at 10nm.

SRAM is only a killer because it is the prime candidate to pack more (junctions) into the smaller area making leakage and bit failure a thorny issue. Couple that with wanting to push hard for ever higher speeds and you have self made (by the industry) issues. For mining ASIC's, as you said they are more robust and if you have a few dead cores, oh well, still a good chip. What has really helped is that only the patterning for making the junctions needs to be done with EUV, by using 20nm features for the intermediate layers the rest of the chip can be built up using very mature processes.

[HyperMega]

<snip>
This would result in about 3200 good dies per wafer. Right?

70000 mm² per 300 mm wafer and assuming 90% yield a single die size would be about 20 mm² (4.5mm x 4.5mm), which would fit to the package size.
<snip>

90% yield?  
That is WAAAAAY off base. That yield is common for higher nodes like 28nm on up but currently 16/14nm production yields are around 40% good dies and lower. They only began to hit 40% late last year...

Now the foundries are of course trying to get better but the processes are still under development. Biggest issue is the EUV light source used for the photo lithography. That monstrosity is still pretty hairy to run and is in no way capable of running 24x7. Is more like 8-20hrs followed by around 6 hrs to a full day of cleaning/realignment/process verification before starting another run of chips.

Sorry, but the foundries still managed to get 14/16nm working without EUV. Currently they are thinking that they need EUV starting with 5nm.

Normally SRAM is killing the yield of new technologies, but there is no SRAM in a Bitcoin Mining ASIC. In general these mining ASICs are very resilient and can also live with some faults. So I#m pretty sure, that one can achieve allready very high yields with a robust design style.

No, the foundries *are* using EUV right now despite the problems. I've worked with the companies involved.

Yes until EUV became better last year they pushed double patterning with conventional light sources far beyond what was thought possible but in no way did it work well enough for what the semi biz calls high volume production. TSMC and GloFo both use 13.8nm light sources while Samsung uses 9.5nm light (which is why they are producing actual 14nm junction chips vs 16nm). The talk of pushing back to the 7 and 5nm nodes was referring to that EUV may be able to work there as well instead of hitting a wall at 10nm.

SRAM is only a killer because it is the prime candidate to pack more (junctions) into the smaller area making leakage and bit failure a thorny issue. Couple that with wanting to push hard for ever higher speeds and you have self made (by the industry) issues. For mining ASIC's, as you said they are more robust and if you have a few dead cores, oh well, still a good chip.

In principle it sounds like you know what you are talking about. But in this case you should also know that GloFo and Samsung have an identical 14nm FinFET node (with identical litho tools).
This deal was made in 2014, because Samsung was looking for a second source and GloFo was struggling with its own 14nm development. Glofo licensed the Samsung technology and brought it up in its US fab (Fab 8 ).

And I'm also pretty sure that there is absolutely no EUV litho involved in the 14/16nm technologies. Just double patterning for the critical masks. (What do you think what I do day by day? )

And no fab would announce ready for volume production if they would only have 40% yield for a typical SoC product like the iPhone 6 processor, which is produced in millions since last year in both Samsungs’s 14nm and TSMCs 16nm FinFET technologies. Do you really think, that Apple would accept 40% yield?
On top of that the iPhone 6 processor is much more yield critical than a Bitcoin mining ASIC, because it includes MBits of SRAM and does not tolerate any logic fault.

Of course, TSMC/Samsung and Glofo have already EUV tools working in their fabs, but only because they are already developing 10/7/5 nm technologies and running first prototypes e.g. to bring up the SRAM yield, which is the first thing they do. The other stuff is easy afterwards.

I'm also not really sure, what you are trying to say.
Something like: "Don’t worry! Bitfury has a super chip, but they can't produce it in volume, because the yield is low and TSMC doesn't care about $10M … $20M revenue."?

[HyperMega]

The talk of pushing back to the 7 and 5nm nodes was referring to that EUV may be able to work there as well instead of hitting a wall at 10nm.

And please read again carefully:

According to TSMC’s Mark Liu, “As you can see in our 7-nanometer development schedule that probably will not using EUV. But we are planning to exercise EUV using the 7-nanometer technology and currently we are planning to use EUV at 5-nanometer. But of course it does depend certain development criteria, milestones to be reached. And it has a good benefit from our assessment on the 7 — on the 5-nanometer that reduce a lot of many masking layers and increase a lot of better control for the 5-nanometer.”

TSMC thinks that they can even handle 7nm without EUV!

[NotFuzzyWarm]

Interesting. I was told by my contacts at TSMC that some of their EUV systems from ASML are now running production and were responsible for the improved yields.

As for Apple accepting 40% yield per wafer, for initial runs - yes. That is between them and the foundries. I guarantee that with their clout they are only paying for the good chips and forcing the foundries to eat the scrap.Their only compensation is that Apple and other customers know that initial pricing will be very high to finance the R&D needed and capital equipment costs. Worse for the foundries is pricing is based on a mandatory rapidly downward sliding price per-chip giving foundries great incentive to get better.

The other little niggling bit pertains to the complexity of the chip. As you said, mobile device processors and such have very little to no built-in redundant circuitry to get around mfg defects. Couple with them being highly dependent on timing of the functions and that can explain the oft-cited in the past low yields.

re: production volumes for mining ASIC's, sure they can produce in volume if Bitfury/Bitmain et al pony up the $$. If the simpler chips make it easier to get higher yield so much the better.

[2112]

The 40% yield refers to number of good chips per wafer - not cores per chip. As to what is a good chip, it one that meets spec. Preferably with 100% cores active @ stated speed. From there they will start stepping down the grade hopefully mainly by speed capability instead of by dead cores.

You start sounding weird... Not enough caffeine this morning? Or too much?

The whole point of mining ASIC is that there's no "spec". It is 100% self-love. All they have to do is twiddle their own little thumbs really fast and gaze at it's own navel. The theoretically most demanding application for them would be if they are daisy chained and have to talk to their brothers from the same wafer or same batch that is sitting few centimeters away on the same board. No need to interface e.g. a DRAM chip or obey some IEEE standard.

The only 3 things that miners care are:

1) Ghash per sec/W
2) Ghash per sec/$
3) delivery time

There's no "stated speed" or "100% cores". Everything else can be and will be worked around at the board layout and software driver level.

[Mr. Kashif]

Well, Well, Well...

Have a look here everyone.


http://www.allied-control.com/solutions/immersion-cooling-container-datacenter

[HagssFIN]

Well, Well, Well...

Have a look here everyone.


http://www.allied-control.com/solutions/immersion-cooling-container-datacenter

See this comment from this thread: https://bitcointalk.org/index.php?topic=1344103.20

Allied Control is not "other people". Bitfury acquired Allied Control some time ago.

[jstefanop]

As for Apple accepting 40% yield per wafer, for initial runs - yes. That is between them and the foundries. I guarantee that with their clout they are only paying for the good chips and forcing the foundries to eat the scrap.Their only compensation is that Apple and other customers know that initial pricing will be very high to finance the R&D needed and capital equipment costs. Worse for the foundries is pricing is based on a mandatory rapidly downward sliding price per-chip giving foundries great incentive to get better.

Exactly...Apple has pretty much financed probably a huge chunk of R&D costs for the last few die shrinks. Their deal probably works something along the lines of "here are billions of dollars, buy the equipment and create the process for x node, and gives us 10 million chips by this date....we don't care what your yield is."

Of course this is a win win for both parties...apple gets its new energy efficient Ax chips first, and the foundries develop a working process for that node and make their profits from the customers of the likes of Nvidia and bitfury

[NotFuzzyWarm]

The 40% yield refers to number of good chips per wafer - not cores per chip. As to what is a good chip, it one that meets spec. Preferably with 100% cores active @ stated speed. From there they will start stepping down the grade hopefully mainly by speed capability instead of by dead cores.

You start sounding weird... Not enough caffeine this morning? Or too much?

The whole point of mining ASIC is that there's no "spec". It is 100% self-love. All they have to do is twiddle their own little thumbs really fast and gaze at it's own navel. The theoretically most demanding application for them would be if they are daisy chained and have to talk to their brothers from the same wafer or same batch that is sitting few centimeters away on the same board. No need to interface e.g. a DRAM chip or obey some IEEE standard.

The only 3 things that miners care are:

1) Ghash per sec/W
2) Ghash per sec/$
3) delivery time

There's no "stated speed" or "100% cores". Everything else can be and will be worked around at the board layout and software driver level.

Um, tell that to the customers screwed by AMT/Bitmine.ch over the A1 kerfuffle when it was introduced. Inno's A1 failing to meet design specs cost us final customers 100's of k$ in total or more. For most folks it looks like their money is never to be seen again as the lawsuits are in limbo. And ja Bitmine.ch's horrible board design was the icing on the crap cake.

BirFury, Bitmain, et al care very much about spec as that is what they base their miner designs on, eg how many chips in it running what speed will give us advertised throughput/power usage.

Sure miner chips are vastly simpler than the various processors used in mobile devices. Just simple I/O, bit of memory, coms and the SHA256 cores vs hundreds of I/O and scads of different core components including critical L1/2/3 cache memory. That simplicity should in turn give more good chips vs yield from making mobile processors and their ilk.

[Mr. Kashif]

Does any one know what testing tool software are Bitfury guys are using in their 16nm ASIC demo vidoe's?

[bronxnua]

I'll probably have to wait for the store to open up, like all the other broke dudes. Sorry, no venture capital here. Dangit Bitfury, stop teasing us with really good stuff!

http://bitfury.com/products#application-form



Apply with them maybe they will send you some chips to test.

[2112]

Um, tell that to the customers screwed by AMT/Bitmine.ch over the A1 kerfuffle when it was introduced. Inno's A1 failing to meet design specs cost us final customers 100's of k$ in total or more. For most folks it looks like their money is never to be seen again as the lawsuits are in limbo. And ja Bitmine.ch's horrible board design was the icing on the crap cake.

BirFury, Bitmain, et al care very much about spec as that is what they base their miner designs on, eg how many chips in it running what speed will give us advertised throughput/power usage.

Sure miner chips are vastly simpler than the various processors used in mobile devices. Just simple I/O, bit of memory, coms and the SHA256 cores vs hundreds of I/O and scads of different core components including critical L1/2/3 cache memory. That simplicity should in turn give more good chips vs yield from making mobile processors and their ilk.

You are just projecting your misfortune. I'll repeat specifications are worth nothing without the appropriate contract enforcement mechanisms, either legal like https://en.wikipedia.org/wiki/Letter_of_credit or extralegal like .

Both Bitfury and Spondoolies have history of not meeting the predicted specifications. But for them and their customers things worked out because they had the right mixture of business and technical skills. I already wrote about Bitfury, so I'm just going to mention that Spondoolies did things like refunds for underperformance and advised customers to use hair dryers to warm up miners that wouldn't start in the cold climates.

[NotFuzzyWarm]

At least I eventually got a rig from AMT even if >4months late and by then nearly obsolete tech Most folks didn't or got them without PSU's.

You are right in that as final users of the chips we could/should care less what the physical chip does vs what design simulations (and any pre-order hype) said as long as it performs as advertised with the typical real-world specs when sold.

Just saying that once a chip is on silicon and in production it can then benchmarked to see what the real world performance is. At that  point any difference between initial expectations and physical product is between the chip OEM and foundry to work out. However once engineering samples are released and folks develop reference designs/actual complete miners based on those proven nominal performance specs it is expected that each chip used does all it is supposed to.

Deviation outside of nominal = either the chip vendors having to under-spec the chip to cover slow ones and use more ASIC's in their mining rigs to assure rig performance  (but in turn make for possible OC'ing) or if production tolerances or tweaked performance expectations per-batch get out of hand then just sell the chips like Bitmain did - different miner batch #'s with different advertised performance. btw: Bitmain has/is compensated its customers for the lower than expected performance batch. I still from time to time get a 0.01btc input to my wallet from them over it.