It is now June.  Time for an update.

It's a PROTOTYPE with HALF the number of modules of the FULL PRODUCT. 

Holy $#!+ what a f&@#in' train wreck.  If this guy actually was who he says he is, he would at least be able to speak the lingo.  

SCAM!  Go ahead prove me wrong.  Send me a board that you designed.  But not one from some other web site you commandeered from a legitimate company.  Hell, even send me PHOTOS of the board you designed.

Still no updates from helveticoin? 

Hmmm... I'm wondering about the KnCminer and ORSoC partnership....

So what's up helveticoin?  Any news yet?

Same here.  Very strange.

I suggest you just wait another month when 1 BTC = 1 oz of GOLD!!    

Since it says "April 1, 2013 end of day Eastern Time", wouldn't that give them until 23:59PM on April 1?  By my estimation, they were 23 hours early.  Perhaps the person who wrote the bet INTENDED to say "March 31, 2013 end of day Eastern Time" but that's not what was written.

Disclaimer:  I had a bet on a different site hoping BFL would ship in March 2013.  I lost that bet.

Similar to the OP, I have no inside information, only that which has been posted on the public forums.  I do have a few points of clarification - based on my limited understanding of BFL's situation.

1) None of the wafers have been wafer-probed and BFL does not have capability to do so.  I would hope and expect they will fix this in the future.  If the die do yield well (say > 95% good), then it is reasonable to skip wafer probe and do a "blind build".  This is what BFL gambled on.

2) Of the first 6 wafers, they choose to "burn" one by skipping the bumping process (because it was causing delays) and use wire bonding to a bare minimum number of the bump pads.  These test die could not be fully tested or run at full speed for the obvious reason that only a few of the power / ground pads were connected.  These die from wafer 1 had good power - at least within the expected range.  They did this while waiting for the other wafers to get bumped so they could verify functionality of the design.

3) Wafer 2 was bumped and packaged.  (Note that wafers 3 to 6 were bumped but NOT packaged at this time.  They should be packaged by now though.)  These are the chips that have been mounted to test boards and exhibit the high power levels. 

4) I have seen nothing posted about the current status of wafers 3 to 6.  It is POSSIBLE that BFL's power issues COULD be limited to wafer 2 and wafers 3 to 6 will have "good" power.  It is well know in the chip business that there can be (and often IS) a variation from wafer to wafer on parameters such as frequency and power.  Of course, the fab tries to minimize these variations, but they do occur.  Especially for the first wafers out. 

5) In addition, there is a variation of different die on the same wafer.  If BFL happened to pick poor die for their test boards, then other die from wafer 2 might be lower power.  However, I do not think this is likely in this instance.

6) BFL has said they will underclock devices to meet a reasonable power envelope and then ship more units to each customer so that they will still receive the GH/s that they ordered.  So if the SC Singles need to run at half speed (30GH/s) to not overload the power circuitry, then a customer that ordered one will actually receive two.  I do not expect there to be a fire problem.

7) BFL has said they are re-designing the boards to improve the power situation.  To me this is unclear what they are doing.  I think Josh said something about using 2 regulators instead of 1 - but I could have that wrong.

The above is true to the best of my understanding but of course could be partly (or completely) wrong since I can only interpret what I've seen on the forums.

Additional disclaimer: As stated earlier on this forum, I have ordered an SC Single.  Yes, I am biased but I try to minimize that bias in all my posts and state as much factual information as possible and remove my opinion from it.

The boards are the easy part.  Any decent college kid can do those. 

What you will not be able to easily acquire are the ASIC chips themselves.  You're looking at a multi-million dollar project (and at least 12 months) to design a chip to be competitive with what will be out there in that time frame.  If it was as easy as you think it is, there would be 20 or more companies selling them already.

Is anyone running p2pool on an rpi?  I would guess the memory overhead of running bitcoin-qt would be WAY too much for the 256MB memory in my rpi (or 512MB in the newer ones) and SD card combination. 

Has anyone done this yet?  If so, what were your results?

It is similar for me.  My understanding is that the luck is bad so payout is bad.  Wait a few days and the luck should get better.  I'm assuming your using DGM not PPS right?

I would concur with this.  The only way it will work is if the guy is able to pull together over $2M in funding and a team of at least 3 or 4 very good chip designers.  (Could maybe be done with 2 very experienced people, but would probably require a team of 6 or more.)  The mask set itself will be in the $1M+ range for 20nm. 

This ignores the fact that 20nm is apparently not available until after his "delivery date".  If I cared, I could check with our fab people on TSMC's real schedule.  But I don't care.

I would like to continue to mine my measly 0.9GH/s on Ozcoin but I cannot get the configuration right after the changes made roughly 9 hours ago.  

Using cgminer 2.11.3 on http://us.ozco.in:8332    (I was on port 80.)

Since my hashrate was so small I was not using stratum and I was under the impression I would not be forced to do so.  Perhaps that is my problem.  Do I have to use stratum on Ozcoin now?

Edit:  Do I need to use "stratum+tcp://" instead of "http://" ?

Hal,

Thank you for all you have contributed to bitcoin and for sharing your story.  Very inspiring.

^^ This.  If I were a bitcoin ASIC designer, I'd send them a photo of my chip, but not a chip.

Can you please add this to the README (that nobody reads)?  

For the record:  From my decades of experience with chip design, I believe BFL's ASIC is real and all that has been stated publicly (including the crappy lengthy delays) is consistent with typical teething pains accompanying a first effort in such a project - especially from a company that has never done it before.  If it is in fact a hoax / scam, then they have REALLY done their homework in generating photos and statements consistent enough to fool me.  However, I am confident that it is real.

Disclaimer: I own one BFL Single (FPGA) and have one SC Single (ASIC) on order.  Although I'm obviously biased, I try very hard to remove that bias from any technical evaluation.

Different chip designs look different - just like different motherboard designs look different.  

Of your 3 photos, I believe the last one is actually a CAD software output of an earlier revision of the BFL ASIC.  I think that was the version for he QFN package.  The newest one that should ship "within 4 to 6 weeks" has a different top layer metal for the BGA package but almost certainly looks the same / similar to this photo if you remove the top layer.

I agree.  5MH/s maybe, but not 5GH/s.  In my opinion, this is probably not worth investigating further.  Of course, it would be great to be proven wrong.  But I'm doubtful.

This looks like a great product.  I have only 1 question:

What happens to my keys & bitcoins if I loose the device or it stops working because my dog chewed on it?