The info is on page 38 section 2.5.6 You have a primary slot that runs at x16(Blue x16_1) 8GB/s = PCIe 2.0 standard for x16 link speed, and a Universal slot x16(Gray 16_2) with a max speed of 4GB/s -or- x8 link speed. It says max x8 link in the picture. The best test will be to plung in both cards and run GPUz tool. It will tell you your speeds, clocks, and temps. Either way, still no problems For more info on PCIe > https://www.icc-usa.com/compare-pci

Talk about thread hijacking Just kidding! I too have ran into this recently. In fact, my linux box will not find any peers available. I've tried swapping libboost around (1.46/1.48) recompiling the latest...same problem. I found a user who was kind enough to setup 3 boxes to help speed this up. add this to your worldcoin.conf:

addnode=198.58.124.238
addnode=106.186.118.114
addnode=212.71.239.66

Just be kind enought to remove them once your all caught up so other people can benefit the same. The true issue is port forwarding related. Port 11081 needs to be forwarded or the coind needs to be compiled with UPNP support.

Thanks go to NutNut here: http://worldcoinforum.org/topic/741-wdc-is-a-joke/

I mine scrypt (LTC,BQC,WDC...) speed is not an issue when side by side. I have a gigabit GA-MA78G-D3SH Phenom X4 9750. It was designed for SLI back in 2008ish. My primary card runs at x16 and the secondary runs at x4. I have the same speed if I flip the cards around. In fact if you look around you'll notice that some people have riser cards. These cards convert your super short PCIe x1 slot into a powered x16 slot. The speed will of course operate at x1 but the work being done inside the GPU and GPU RAM is not affected by this. I believe the card cannot produce hashes fast enough to need more bandwidth. Your basically plopping a job on the stack and the card works through it and transfers the answer back. GPU workload is not based on how fast you can load work onto the card but how fast can the card push through the work. That is the bottleneck. So x1 shouldn't matter, but keep reading the forums for a consensus. Or someone correct me if I'm wrong.

Your PCIe slots are based on the motherboard chipset. They used to be North bridge, South Bridge but now Intel and the others are producing PCH(HUBs). We have 1 chip instead of 2. This chip is what has the USB, PCIe, PCI, I2C, SPI, UART, DMI, SMBios, RTC, GPU...... all of the busses and devices. The best place to start when trying to determine how the slots are tied together is your manufactures manual for that board. It will tell you if SATA ports 4+5 are shared with the Primary IDE controller and how your PCIe slots operate together. Here is a blurb from my board.


    1 x PCI Express x16 slot (Note 3), running at x16 (PCIEX16_1)
    1 x PCI Express x16 slot, running at x4 (PCIEX4_1) (The PCIEX16_1 and PCIEX4_1 slots conform to PCI Express 2.0 standard.)
    3 x PCI Express x1 slots (The PCIEX1_2 and PCIEX1_3 slots share the same PCIe bus with the PCIEX1_4 slot) (Note 4)
    2 x PCI slots

Whatup miners and ops. I've been lurking around for awhile and I finally created an account to join the fun here. I usually don't post unless I have relevant important info. I'm pretty good at researching so I usually don't have many questions to ask. If I find the answer then I will say something and help out others. That's what makes the world better right? Other than that I am a miner, programmer, electronics enthusiast, and more. I enjoy the constant modding and recompiling to get that perfect solution. I tried digging into some source for all these different coins and whew is that alot of code. Most of it seems to be cloned from coin to coin. I've setup my own personal pushpool and stratum for BQC and WDC. BQC doesn't support getblocktemplate yet so thats depressing. I am trying to incorporate vardiff and stratum into the BQC daemon but nothings concrete so far. I run 4 small rigs and plan on expanding like the rest of the population. Well that about sums it up. I could keep going on a tangent but I'll save it for later