It would be nice for someone to join me in developing bitstreams for Kintex-7 FPGAs.
I have used the open-source FPGA code with the 7K325T-2 device on KC705 board and have programmed it to hash at
600MH/s (600MHz) with
~30% device logic usage using fpmaminer's code that uses almost all the
DSP blocks on this FPGA.
Please PM me if you want this bitstream / source code.https://github.com/fpgaminer/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/KC705_experimentalThe board costs ~1700 USD + tax from Avnet and has support for external DDR3 RAM which could potentially hash
scrypt, though it's a speculation at this moment. The board also comes with a full seat of ISE + Vivado locked to this FPGA.
The chip and Vccint VRM of this board heats up a fair bit at that clock speed, but if kept near an AC vent the device runs stable for many days.
Another user has suggested using VGA memory heatsink blocks on the VCCint VRM inductor. I will try this as soon as the heatsinks arrive.
The first order of business would be to instantiate another set of hashers so that we can get towards full device usage and monitor power consumption, and heating issues if any.
This way we can try to reach ~1GH/s and more on a 28nm FPGA board with good availability.
If you fulfill any one of the following, and have some spare time at hand, it would be great if you could join me in this project.
a) Ownership of a Xilinx KC705 board. This is a decent FPGA board with a 7k325 -2 FPGA
b) Xilinx Vivado tool / ISE tool running
c) Fluency with HDL code.
Some leads to start from
https://github.com/fpgaminer/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/Kintex7_160T_experimentalhttps://github.com/fpgaminer/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/VHDL_StratixIV_OrphanedGland/sha256/rtl
PS. I am located in SW USA.
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