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Hi,
synchronization of blockchain is very slow above height 300+
Is there any direct way to speed up, with use fully synchronized blockchain of Bitcoin Core, running on the same subnet ?
Adding BC as peer doesn't help with speed ...
Exists any tool to convert db's ?
Thanks
R.
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I'm playing with getblocktemplate, provided by client. I wrote simple proxy between breakoutd and cgminer, but all my mined block was rejected. I searched why and I found my math is wrong. For example, block 14814 has only 1 tx == coinbase tx: coinbase = '0100000028c8be57010000000000000000000000000000000000000000000000000000000000000000ffffffff0602de39025901ffffffff0100f2052a01000000390000001976a9147d1f3b8b8d5be1353f08acb780780076d188ef6688ac000000000000000000' Then: coinbase_hash_bin = hashlib.sha256(hashlib.sha256(binascii.unhexlify(coinbase)).digest()).digest() and def build_merkle_root(self, merkle_branch, coinbase_hash_bin):
merkle_root = coinbase_hash_bin
for h in self.merkle_branch:
merkle_root = doublesha(merkle_root + binascii.unhexlify(h))
return binascii.hexlify(merkle_root) binascii.hexlify(coinbase_hash_bin) results b1a713d3a3f4cf04ddec887223bb723eb15202edd306a5f8d6ea333fd59027a0and merkle_root == coinbase_hash_bin for this block Expected merkle root is 4d6d8cad90a9d97f2755d228e4c0764e10774b8511f99e86ef75679607341f58What is wrong? Thank for help. |
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Does anyone know when Breakout will be availbale on Linux? I want to stake with BRX on my linux server
I compiled from source the other day on 14.04 and it is working fine. Version is 1.4.3. -tb- where did you get source code? thx R |
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What's wrong with eth minning?
My earning was about 1,68 - 1,7 eth per day.
Last day or two is it 1,4 eth/day.
It's about 17% drop in two days!!!!
Calculator shows for 220 MHs ~ 1.69 eth/day.
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Username: Roller
User ID: 15242
Thanks
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but, a single chip should produce 330mhs not 110 Tbh I think we're too late with avalons...If I get some fury chips fancy doing it with them ?  Also percentage of rejected shares looks terribly. But i think it's no problem. I think it depends on time of measurement. Look, there is cca 7,5 minutes uptime. I use slush's pool and it's the same with my fpga's & asics... simply: measurement, based on accepted shares is crappy and results are real after long time .. let's say 5-10 blocks of hashing .) I think, explorer got enough skills to get bitfury's chip hashing  |
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Hi, Blue line represents REPORT_N and yellow REPORT_P
so IDLE, SEND1, SEND0, SEND1, SEND1,SEND0,SEND1,SEND1,SEND1 = 0xED - LSB BYTE
0xF78A00ED is received nonce
heh .. my bad point of view  |
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Hi Explorer232,
I tried to decode part of nonce, showed on picture.
If I'm right, the sequence from left to right on the picture is:
IDLE, SEND0, SEND1, SEND0, SEND0, SEND1, SEND0, SEND0, SEND0 it means 01001000 == 0x48h
But in LSB scheme it means 00010010 == 0x12h
It isn't part of 0xF78A00ED you decoded.Correct me if I'm wrong.
Or 0xF78A00ED is golden nonce = received nonce - 0xC0?
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If I see right, each hashing module in reference design got 20pin (10x2) header. Most of pins are connected to Vcc and GND. The most interesting signals are two diferential pairs config and report. Chips on hashing module are connected serial on config, and parallel on report. And it's I wanna try to connect to FPGA's IO in the first step with single chip or couple of chips. Of course I have to connect Vcc, GND and CLK to chip.
The next step may be a simple reduction between FPGA-based machine and reference design's hashing module, or another hashing module.
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Project: Avalon controller Hi, I'm sw developer and hw hobbyist. I started working on avalon controller, based on existing FPGA-based mining machines, which become unusable for bitcoin mining in near future. Some of them are designed as development boards, so they have FPGA's IOs achievable. I want to use FPGA-based machine as completed avalon chip controller. The main work is to create FPGA's bitstream, which isn't opensource this moment in Avalon's reference design.  Features: - Opensource - Direct USB connection - Modularity - Can operate up to 16 hashing boards simultaneously ( ... or more, depends on available IO's) - Easy update via JTAG Please note, this is my free-time project so if someone wants to support this project may send me some coins .) Thanks. Donation Address BTC: 1D9qCCQUykPo8hZZd1bFxC1PRg3sjiQSqS |
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And your post is most stupid I read here. Do you have any chip? I don't think so. Why did you respond here? It looks like you're just the internet troll and +post hunter. meeeh, honestly one of the most stupid thread, that I ever seen on this board. please follow: https://bitcointalk.org/index.php?board=137.0and ask some group buy owners, if they have got any spare sample chip (I'm pretty sure, that they will provide you something, only if you prove some progress and show base project description/PCB layout etc.) good luck anyway Is there any obtainable avalon sample chip for development of simple miner board?
If you can provide any, please PM me.
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Is there any obtainable avalon sample chip for development of simple miner board?
If you can provide any, please PM me.
how can u ask that ? were u offline in the last 2-3 months or u're just too lazy to read? Registered May 10. I read many of threads, yet I'm asking. Do you have any problem with? Can you help or are you only troll? |
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Is there any obtainable avalon sample chip for development of simple miner board?
If you can provide any, please PM me.
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The datasheet is rather vague on some points. The HDL would help very much. Or probing a running ASIC on a board... intron Yes .. i read datasheet and I couldn't find, how the report n, p timing is done. Friend of mine has sample chip, he can send config and sample data into chip, it calculates golden nonce, but output has some strange timing. It look like it's derived of external oscillator frequency, but how? |
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Great!!!! Can't wait for first accepted share ;-)
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Hi, explorer232, greetings from Czech Republic!!! As we talked here before, I'm definitely interested. I made a little simple investigation about return of invested capital and avalon looks good for now. (Real parameters will be different, but for imagine and comparison it's enough.) I have to say I don't know details of your design, but there is possibility of overclocking, as described in datasheet of avalon chip. (And discussed in other avalon-clone threads like this). Did you think about possibility of supply voltage/clk frequency tweaking? And second note, please think about 28(-35)GHs variant, I mean 10 avalon modules shield. You always can use 3 modules only, but benefits of modularity are known ;-) If I can provide you any help, feel free to ask. Ramirez |
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Ngzhang provided a dev usb stick with his Icarus (Lancelot) board. But the projects are discontinued. Can anyone share the content of dev usb stick?
Please PM me.
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