For an application like this, a monolithic PSU is the way to go. The one roybitcoin suggested looks good, is only $1.72 in 1-piece prices, but only puts out 1.5A and is a package that cannot be soldered by hand (would need a reflow method).

I will dive into your schematics later today and see if I can come up with some values for your PSU, and do some digging for a suitable monolithic equivalent.

Dead wrong. You know there are 7 billion people on Earth right?

Maybe: "Most people who have money to invest in risky ventures have heard about bitcoins by now."

Care to back that up with proof?

Holy crap mega buy to $144+

what is this i dont even

I agree. So here's a chart. I put a line on it.

Ah, new information (to me)! This is very helpful.

I'm usually not one to speculate on such things as a chip pinout, but allten seemed eager to have more information, perhaps to move a little further on his pcb layout.

I'll agree the top pour has to be Vcor, and that 7,24,37 are most likely Vio.


I spy with my little eye, an XO! On the card, look at the space below the backplane connector. There is a metal can smt chip that has the writing "TXC 32.0 CBB3V" on it. Looks an awful lot like:
http://www.txccrystal.com/images/pdf/7w.pdf

If it is indeed a 32MHz signal, that would support my idea of single ended clock lines (pushed by the little 6-pin buffer lookin' guy below the xo).

Wow this thread really exploded. Unfortunately, I couldn't get myself to read it all (just allten and burnin's posts)   

Anyway, with regard to Avalon ASIC pinout, if it would be any help I can give you informed guesses for some pins:

Guesses are based on: https://en.bitcoin.it/w/images/en/c/cb/Avalon-detail.JPG


1. GND pins -- assuming the chip side copper pour is gnd (more on this after), you can see that pins (counter clockwise from pin 1 dot) # 3,4,6(?),11,12,13,14,15,16,19,21,22,25,26,27,28,31,33,34,39,40,41,43,46,47,48 are connected to the pour.

It is equally likely that these pins are for PWR, since it is highly likely that the thermal pad is the singular (or at least the MAIN) GND. Thermal pads being connected to GND is standard practice.

HOWEVER, placing two decoupling caps near each other that are a decade apart in capacitance is a common way to get rid of a wide band of PSU noise. I see this at pins 7,24,37. Three 10-mil traces could easily carry 2A (=2.4 watts) with ~10C rise in trace temp. This could mean that the top copper pour is indeed ground.

2. CLKin signal speeds -- I believe the clock feeding the Avalon is lower speed (hinting at an internal PLL/divider). This is more of a guess. In the above photo, you can see an exposed test point titled "CK," common shorthand for CLOCK. Since this is single-ended, it is likely that the line is below 100 MHz.

However, this could simply be a test point/pin for an internal LO, and the real clock signal could be coming in differentially on any of the pairs that look purposefully impedance-matched (1&2, 17&18, 29&30), though I think its more likely that these are data lines of some sort.

No risk, no reward.

Smoothie, why are you being so cruel to BFL customers? Was everyone screaming bloody murder that BFL was going to be 7 months late on their delivery when they were accepting BTC preorders? Everyone putting any money into any mining venture is taking a risk. Sometimes those risks don't reap rewards.

disclaimer: i haven't put any BTC into any of my mining-related activities, except maybe some stuff from cablesaurus.

Interested, but MORE interested in hearing about your dev team.

"If it was easy, everyone would do it."

samurai1200; 30; 2.58; 12ST2a5E9AfsBGgmTpLDt9FLVR5yC8QsqB



https://blockchain.info/tx/48669b0f91d5f9acf9565c5303dd253bacdd67399f14db0b040576721040c246

@Big Time Coin,

I saw in another thread that you are having trouble hiring engineers.


I think that's only partially correct (your claim stemming from the sentiment that Bitcoin could ultimately be an ephemeral thing). I think the biggest part, however, is:


I know that I was very excited reading this up to this point in the job ad (and I currently have a job as an EE). But, well, its very nice (albeit expensive) living in California. 

I know that contracting engineers out of state may be unsettling, but if you define the conditions correctly (i.e. always be available to call/email/Skype during certain times, required daily/weekly reports, etc.) it may be less of an issue than you think. Anyway, it may be the only way you can gain traction in hiring.

I wish you luck! I'm planning on designing my own small Avalon ASIC-based device, with a focus on being sexxxy. 

Soon as that datasheet hits, its gonna be an all-caffeine, no-sleep kinda month....

1.06 BTC sent.
https://blockchain.info/tx/03339a19d35bffc8f9ab9ccb7e7c996af41548a4ac7be6662bb3140d2acb2dc8

(not sure why blockchain wallet sends the remainder of that address to itself. is that a bitcoin thing or a blockchain thing?)

Doesn't a downward consolidation after a rally indicate a continuing rally?

   

I "grew up" on OrCAD 10 through 15, which had tons of bugs and quirks but was powerful once you knew how to work around them. For the past 2 years I've been using Eagle at work and home. I have not had the chance to use Altium, PADS, Pulsonix or others. Altium seems to be the de facto standard these days, but seats are SO EXPENSIVE.

I've gotten used to hand-routing everything anyway (used to do a lot of analog design), so Eagle is fine for me. Luckily I haven't had to do too much impedance-controlled lines, and what I have had to do I've just calculated/routed by hand.

My guess is yes, since the whole of whats inside a digital ASIC can be done fully on an FPGA first (hence less time/effort in producing PCBs to test analog sections). The only difference is that a FPGA would be less efficient than an ASIC would end up being (obviously). But this can all be accurately simulated.

So chop my numbers in half and they start approaching the Avalon pre-order range.

[edit] Ah, so based on what BkkCoins said, he had a little capital from the Icarus project. Add that to preorders cash and previous FPGA bitstreams, and he probably developed the Avalon ASIC for 250k or less.

@pizza's OP:

For a typical new-tech ASIC, 600k-1M seems reasonable.

I have been through a couple ASIC design cycles at my last job (longwave data receiver, which is arguably much different than a purely digital ASIC like Avalon's/BFL's). As the company was small, as an engineer I was also part of the budget meetings. It cost roughly 1M to get to our first working ASIC wafer. 400-500k went to development and the engineering runs of chips. First, everything was "simulated" on a mix of FPGA hardware (for the digital side of things) and analog hardware (for signal reception/analog side of things). About 250k went into the first two engineering wafers (first prototype batch, first revision batch), and the remaining amount 250k-ish went into manufacturing 10k chips + verification and validation hardware. Built into these numbers is roughly 1 year of employee salaries (there were roughly 10 of us working on this stuff).

So yeah TL;DR is 1M total, where 50% is employee costs, 50% is manufacturing costs (including ASIC fab and PCBs and whatnot).

At work (where I am an EE doing PCB design), I or my assembly ladies routinely solder down QFN-28 + thermal pad packages (careful use of a hot air gun). With my current order (12 chips), if I plan on making the PCB myself, for myself, I'll probably go this route. If I find that there's interest in my board on this forum (as I'll also be doing microcontroller firmware and PC interface also), then I'll probably open up a service where I do a batch assembly order (for BTC!). I would imagine theres a bazillion others on this forum planning on doing the same thing though. So it might end up that I just use their services.

Once Avalon releases the necessary information (essentially an app datasheet for the Avalon processor), I'll likely be developing applications for single chips ("just plug it in to USB and go"), 4 chips, and 10 or 12 chips (depending on data bandwidth scalability of common 32-bit processors). Again, I would imagine many people on this forum are planning the same. Lotta bright people round these parts.

But for now, we're all just salivating over the idea of the Avalon processor app note/datasheet.

Bitcoin enables trustless payments, but unfortunately some things still require trust. When someone figures out the 'Bitcoin' of handling physical goods, we will reach reach the next level of humanity.