As a little encouragement, here's a decent run for my old design (ISE synth+map+p&r, letting synth infer shift regs, no placement constraints, ...) for -3 speed grade
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 92,964 out of 184,304 50%
Number used as Flip Flops: 92,819
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 145
Number of Slice LUTs: 62,141 out of 92,152 67%
Number used as logic: 34,288 out of 92,152 37%
Number using O6 output only: 21,087
Number using O5 output only: 424
Number using O5 and O6: 12,777
Number used as ROM: 0
Number used as Memory: 2,721 out of 21,680 12%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 2,721
Number using O6 output only: 450
Number using O5 output only: 0
Number using O5 and O6: 2,271
Number used exclusively as route-thrus: 25,132
Number with same-slice register load: 25,117
Number with same-slice carry load: 15
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 16,519 out of 23,038 71%
Number of LUT Flip Flop pairs used: 62,163
Number with an unused Flip Flop: 2,573 out of 62,163 4%
Number with an unused LUT: 22 out of 62,163 1%
Number of fully used LUT-FF pairs: 59,568 out of 62,163 95%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%
...
Total REAL time to PAR completion: 19 mins 45 secs
Total CPU time to PAR completion: 20 mins 34 secs
Timing:
================================================================================
Timing constraint: TS_coreclk = PERIOD TIMEGRP "tncoreclk" 182 MHz HIGH 50% INPUT_JITTER 0.2 ns;
3102658 paths analyzed, 386321 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 5.262ns.
--------------------------------------------------------------------------------
Paths for end point XLXI_A/rb20/regt1_31 (SLICE_X104Y33.CIN), 252 paths
--------------------------------------------------------------------------------
Slack (setup path): 0.232ns (requirement - (data path - clock path skew + uncertainty))
Source: XLXI_A/rb19/outE_17 (FF)
Destination: XLXI_A/rb20/regt1_31 (FF)
Requirement: 5.494ns
Data Path Delay: 4.928ns (Levels of Logic =
Clock Path Skew: -0.111ns (0.620 - 0.731)
Source Clock: coreclk rising at 0.000ns
Destination Clock: coreclk rising at 5.494ns
Clock Uncertainty: 0.223ns
Clock Uncertainty: 0.223ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.200ns
Discrete Jitter (DJ): 0.233ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: XLXI_A/rb19/outE_17 to XLXI_A/rb20/regt1_31
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X126Y28.BQ Tcko 0.408 XLXI_A/rb19/outE<19>
XLXI_A/rb19/outE_17
SLICE_X115Y27.A4 net (fanout=8) 1.658 XLXI_A/rb19/outE<17>
SLICE_X115Y27.A Tilo 0.259 XLXI_A/rb20/s1<6>
XLXI_A/rb20/s1<6>1
SLICE_X104Y27.CX net (fanout=1) 1.798 XLXI_A/rb20/s1<6>
SLICE_X104Y27.COUT Tcxcy 0.093 XLXI_A/rb20/regt1<7>
XLXI_A/rb20/Madd_s1[31]_ch[31]_add_18_OUT_cy<7>
SLICE_X104Y28.CIN net (fanout=1) 0.003 XLXI_A/rb20/Madd_s1[31]_ch[31]_add_18_OUT_cy<7>
SLICE_X104Y28.COUT Tbyp 0.076 XLXI_A/rb20/regt1<11>
XLXI_A/rb20/Madd_s1[31]_ch[31]_add_18_OUT_cy<11>
SLICE_X104Y29.CIN net (fanout=1) 0.003 XLXI_A/rb20/Madd_s1[31]_ch[31]_add_18_OUT_cy<11>
SLICE_X104Y29.COUT Tbyp 0.076 XLXI_A/rb20/regt1<15>
XLXI_A/rb20/Madd_s1[31]_ch[31]_add_18_OUT_cy<15>
SLICE_X104Y30.CIN net (fanout=1) 0.003 XLXI_A/rb20/Madd_s1[31]_ch[31]_add_18_OUT_cy<15>
SLICE_X104Y30.COUT Tbyp 0.076 XLXI_A/rb20/regt1<19>
XLXI_A/rb20/Madd_s1[31]_ch[31]_add_18_OUT_cy<19>
SLICE_X104Y31.CIN net (fanout=1) 0.003 XLXI_A/rb20/Madd_s1[31]_ch[31]_add_18_OUT_cy<19>
SLICE_X104Y31.COUT Tbyp 0.076 XLXI_A/rb20/regt1<23>
XLXI_A/rb20/Madd_s1[31]_ch[31]_add_18_OUT_cy<23>
SLICE_X104Y32.CIN net (fanout=1) 0.003 XLXI_A/rb20/Madd_s1[31]_ch[31]_add_18_OUT_cy<23>
SLICE_X104Y32.COUT Tbyp 0.076 XLXI_A/rb20/regt1<27>
XLXI_A/rb20/Madd_s1[31]_ch[31]_add_18_OUT_cy<27>
SLICE_X104Y33.CIN net (fanout=1) 0.003 XLXI_A/rb20/Madd_s1[31]_ch[31]_add_18_OUT_cy<27>
SLICE_X104Y33.CLK Tcinck 0.314 XLXI_A/rb20/regt1<31>
XLXI_A/rb20/Madd_s1[31]_ch[31]_add_18_OUT_xor<31>
XLXI_A/rb20/regt1_31
------------------------------------------------- ---------------------------
Total 4.928ns (1.454ns logic, 3.474ns route)
(29.5% logic, 70.5% route)
Show Posts
