QFP is possible to solder by hand but BGA is not. You will need a special tool and some experience to solder BGA, or pay someone to do it for you. People have soldered BGA with blow dryers before Not that that is the best idea, but just sayin'. Then again, with the complexity of SHA256, gate propagation problems will probably force us to run the chips slowly enough that heat won't be the limiting factor. It's not a huge problem, but it's there. The latest design gets 100MH/s (@100MHz) and requires either a lot of air-flow or a heatsink. you can program the fpga/tiny12/eeprom directly via ISP/JTAG. during development you configure the fpga directly via JTAG from your PC I only looked at the circuit image you posted, not the rest of it, so excuse me if I missed something obvious, but why is there an ATtiny on there? FPGAs can program themselves from a flash chip unless I'm mistaken.
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Would a more generalized SHA256 ASIC have dual-purpose for a security firm or similar, assuming a controller could handle enough of the logic for hashing? Or is the whole point of an ASIC to make it as highly specialized as possible to get optimal efficiency? Probably what kokjo said, but I wouldn't rule out the possibility of making it more generalized. The algorithm can be optimized specifically for Bitcoin, and there are benefits to that which include both increased ASIC performance and reduced cost. What one would have to do is determine how much interest by non-Bitcoin parties there would be in such a chip, and if the cost benefits lost due to supporting a more general approach are out-weighed by the increased demand. Also, it might be a good idea to keep the ASIC general simply because of risk. If Bitcoin fails to meet exceptions during the production of the ASIC chips, the manufacturer would at least have chips that could possibly be sold into other markets. On a somewhat related note, I'd like to stress that I greatly believe any ASIC developments should all be done in the open, with open-source/open-hardware licenses on as much of the process as possible up to and including the free release of the masks. Now, that's a pretty bold statement, since the masks are very expensive. But if, for example, the entire venture is publicly funded that might not be such a crazy idea.
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I made little to no modification to their code for this first commit. If you appreciate their hard work on this Open Source project, please send them your thanks and donations!
TheSeven: 14Jc8vWq1mPv7vWnP5VquZZgpLEtzW2vja teknohog: 1HkL2iLLQe3KJuNCgKPc8ViZs83NJyyQDM
fpgaminer: 1NT4RyJMqtRuDRr6zHdXdKSpmX3SR5he6zThanks to the three of you for your work to date! Plonk, plonk, plonk. Heh, thank you njloof I really appreciate that. Quick update: I've been working with makomk's modifications and they do appear to be giving the performance increase and area reduction quoted. In fact, I saw ~75K LEs when I synthesized. Power consumption was estimated at 4.7Watts. Very impressive work! I'm doing another compile now and will do a live hardware test soon, to confirm correct share submission to mining pools. EDIT: Just tested the new code on live hardware (DE2-115). Works great
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We need nodes so payments can get processed! Payments are processed by the generation of blocks, which is done by miners. Client nodes have no impact on the way payments are processed.
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I've got a coupon here for a free copy of DiRT 3. Came with a Radeon card I won at E3 Retail price of the game is $49.99 at Steam right now, so PM or post your offers in BTC. Thank you!
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June 12th, 2011 - Xilinx and VHDL Ports AddedWith many thanks to TheSeven and teknohog, their code has been added to the public repo. TheSeven did a re-implementation in VHDL, with support for Xilinx and ISE. teknohog did a straight port of the Verilog code to simply support Xilinx and ISE. Both include Python miner control scripts, and serial port communication with the FPGA board. I made little to no modification to their code for this first commit. If you appreciate their hard work on this Open Source project, please send them your thanks and donations! TheSeven: 14Jc8vWq1mPv7vWnP5VquZZgpLEtzW2vja teknohog: 1HkL2iLLQe3KJuNCgKPc8ViZs83NJyyQDM Some notes on the current state of this projectAs it stands now, the project makes lots of references to the DE2-115 board, and it being the preferred mining platform. Obviously this isn't the case, nor is it meant to be an advertisement. It was simply the first device supported, and the one that currently has a binary release available. In the near future, I will merge in full Xilinx compatibility changes into the main Verilog code and try to steer the project towards supporting many devices and boards in a Plug-and-Mine fashion (like the DE2-115 currently is); or at least Compile-Plug-and-Mine Also, the directory structure in the repo is not optimal, but that will improve with time as I settle on a structure that fits the project's many needs (multiple code variations, and multiple device specific implementations). I have many other promising patches to merge, including a few of my own So keep watching this thread!
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Great work OrphanedGland And thank you for opening a thread in the Newbies section. It will be a pain to keep track of yet another thread, but I guess it is our only option for now. If you want, I will happily put your code up on the public repo, if you want it available on there.
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Hmmmm. It looks like Xilinx's synthesis tools aren't very good at inferring the right meaning from various constructs this uses. I'm now seeing if I can convince them to interpret it in more efficient ways, but to be honest it looks like they may just be slightly rubbish. It ought to be possible to cram a full hashing pipeline into a XC6SLX75 in theory, but the current code isn't even getting close. Yeah, I'm still fighting with ISE. Using SmartXplorer I got ISE to P&R a fully unrolled mining core into my 6SLX150 chip at 50MHz. ~50% resource consumption all around, which is good. Two problems: A) results returned by the running core were erratic, and B) the chip ran very hot. Slow progress, but progress none-the-less.
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I'm curious if there are enough Bitcoiners attending E3 in Los Angeles this year to warrant a small meet-up? I think it'd be fun to at least hang out a bit at the show and shoot the breeze. It's a bit late to be asking, since tomorrow (Thursday) is the last day
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If nothing else changed in the design, it may have just been that the seed the tool started with when running it's algorithm changed. Yeah, I know about the random seed, but ... I dunno, that seems too far fetched that the random seed would let it go from completely un-routable, to routing in a few minutes. Then again, I haven't used ISE in a few years, so it may be a lot more temperamental than I remember. I only did one thing different. I ran each stage one at a time, instead of telling it to P&R and have it automatically invoke all the necessary steps. I've been trying to run the verilog version of the code through Synplify Pro Ughhh. I've got an old version of Synplify Pro that refuses to synthesize the design. First, it didn't like the use of block names and last I left it, it was optimizing out the entire design, for no particular reason. I might install their latest eval version on a different machine and see if that version has better luck.
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I think you mean it found shares, unless your running a mining farm with a bunch of computers, if you find 3 blocks in a few minutes that should be a problem. but then again a finding a few shares every couple of minutes isn't really a problem either. I run at about 85000Khash/s and i find a share on average 2-3 minutes. Nope, I mean blocks. I threw ~3GH/s at it for a few minutes, and it was running against testnet (Difficulty == 38). Running against pushpool, I got tons of shares but very few blocks (2 blocks with >1000 shares). Running directly against bitcoind it found 3 blocks in a few minutes.
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I experienced an odd problem with pushpool. I got it setup, and accepting shares against a bitcoin --testnet client setup correctly with RPC. So, everything appeared to work. I even found a few blocks, and those submitted fine. However, at a difficulty of 38, and >1000 shares, it had only found 2 blocks. That's either really bad luck, or something was broken. So I tried pointing the miners at bitcoind directly, and they found 3 blocks in a few minutes (as expected for the hashrate).
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or possibly an Xtreme Data XD-PCIE3000 with three Stratix IVs per card? What size Stratix IVs are they? I don't know how much better the performance of the Stratix parts are. I'd just guess 1.5x faster, so you'd get ~1.5 MH/s per 1,000 LEs compared to the Cyclone series. Maybe more. Maybe less. * DATA is the block header for which a hash must be found. It does contain the unix timestamp. It also contains the current target value, so that's probably where the FPGA learns it (or it doesn't care at all and this is checked on the tcl-side). The nonce is set to 0x00000000. The FPGA doesn't care, it just returns nonces that make a hash meet the Difficulty 1 target (H == 0). And no, it isn't checked on the tcl side either. All pools currently operate on Difficulty==1. For solo mining, the script will submit the data, bitcoind will check it, and return an error if it wasn't below the target. So, not too much harm done there. And yes, I've run it solo before, against namecoind It found a couple blocks! TheSeven: That is some great work you're doing there! I'm glad someone is making a lot of progress with Xilinx devices and Python mining scripts. I haven't had the chance to push your code into the public repo yet, but it is most certainly on my list of things to do. As a side note, for reasons I cannot understand, my design passed P&R yesterday, even though it failed the last time I tried it. This was a half-mining core (only one SHA-256 pass), at 50MHz. I haven't tested it or anything, but ... I'm just bewildered why it routed without any problems this time. I must have done something wrong the first time. Hopefully it isn't just messing with my head, and I can finally start mining on my SLX150. I'd also like to start testing the DSP48A1 slices, which are rated for 250MHz operation and will perform 48bit + 48bit addition
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time = difficulty * 2**32 / hashrate Or, in days: Average Days To Generate Block = Difficulty * 49710.2696 / hashrate So, if you have 1MH/s, and difficulty is 550,000, then: 550,000 * 49710.2696 / 1,000,000 = 27,340 Days
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Since it hasn't been made clear:
1 Megahash / second == 1,000 Kilohash / second == 1,000,000 hash / second
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There are currently 81,545 more blocks until the reward is halved. At a rate of 7 blocks per hour (it's supposed to be 6, but we've been averaging much higher) that's 485 more days. Man ... I wonder what Bitcoin will look like in a year's time.
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I've found 3 blocks @ deepbit Is there a way to look this up on deepbit's website? I'm kinda curious how many blocks I found I've recently switched to solo mining, and I'm praying it's actually working correctly right now My 95% probability is 17 days, or 5 days on average, so if I don't find a block in two weeks I guess I fscked something up
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it reports 48C for the junction temperature. I might just keep it at 50 to be safe. Altera commercial FPGAs are rated for 85C JT.
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It worked! There was enough room left to add a blinking LED when it finds the golden nonce. Just. Yay! It seems to be reporting an Fmax of 82.31Mhz. Is this actually safe without a heatsink? It isn't on the C4-115 chip, but for the tiny C4-22 it might be. Check with PowerPlay. Make sure no heatsink and no fan is selected, and the toggle rate is ~65%. See what it says the JT is. The computation of future rounds of W Well I will certainly double check my math, but you can most certainly compute some of W after the initial 16. Example (0 indexed): w[16] = w[0] + s0(w[1]) + w[9] + s1(w[14]) All those values are known and do not change during the course of a work unit. The same applies to w[17] and w[18]. I don't have my notes with me for the rest.
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