Switching cores off is a useful technique to be used on chips that have huge die sizes ( 200mm2 and up ) where defect probabilities go up and for each defect you either have to throw a very expensive chip to bin or do something else that also might cost big money. The disabling a core is also an expensive solution because it needs a lot of engineering and testing.
I believe this is not useful for BFL because the die sizes are so small making each chip so cheap to produce that is much more economical to just throw the faulty ones to bin rather than trying to do something clever with them. The small die size also means that defect probabilities are much smaller than on bigger dies as the defect probability is some constant multiplied with the die size.
Pulling some numbers from my ass: Not being able to switch cores off could cost them 50 chips each worth $3. How much engineering would you like to do to save $150? The situation is totally different if we are talking about saving 10000 defective chips each worth $200.
The engineering required is near zero. Basically a gated clock buffer instead of plain clock buffer. And a single register wide enough to store those "clock enable" bits for each hashing core.
The overall design is extremely repetitive. The first constraint is thermal. The second one is power distribution rail bounce caused by the huge number of simultaneous switches. Gating the clock would be a standard hardware debugging technique for such a project. I could say that
not including clock gating would be a design mistake. The primary objective is to facilitate debugging. Defect tolerance is an additional benefit obtained for free.
Again, the chip is so repetitive and so self-testing, that standard debugging aids (like JTAG) are nearly worthless. The chip is almost an analog or mixed-signal power chip: the primary constraints are thermal and parasitic impedances.
Edit: Furthermore, I think none of the Bitcoin ASIC manufacturers can afford to invest time and money into a proper chip testing. I'm thinking that all packaged chips will be soldered into the mining boards and the final testing will be in-situ. I don't even think that an investment into the proper test equipment would be worthwhile from the engineering point of view. All in all, those chips are just lottery ticket printing machines, it doesn't make sense to test if some rare tickets are missing or mangled. Each winning ticket is worth something for just a couple of minutes maximum.
