Howdy.
I'm trying to build mining firmware for one of my altera fpga boards based on the ztex firmware. I'm targeting a cyclone3 as it is what I have to play with. I'm using the latest ztex firmware (ZtexBTCMiner-120417.tar.bz2) that is unmodified save the top-level. I'm getting build errors in the sha256_pipe2_base module.
I know enough verilog to be dangerous but not enough to figure this out any time soon.
I am hoping that someone else has run into this (porting to an altera device) before.
Does anyone have an idea of what's going on and (hopefully) how to fix it?
Thanks in adance!
-Marty
Here's the error message:
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition
Info: Processing started: Thu Jun 14 23:16:17 2012
Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition
Info: Processing started: Thu Jun 14 23:16:17 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off c3_miner_usb -c fpgaminer_top
Warning: Parallel compilation is not licensed and has been disabled
Error (10170): Verilog HDL syntax error at sha256_pipes2.v(89) near text "["; expecting "}"
Error (10170): Verilog HDL syntax error at sha256_pipes2.v(89) near text "["; expecting "<=", or "="
Error (10170): Verilog HDL syntax error at sha256_pipes2.v(91) near text "["; expecting "}"
Error (10170): Verilog HDL syntax error at sha256_pipes2.v(91) near text "["; expecting "<=", or "="
Error (10170): Verilog HDL syntax error at sha256_pipes2.v(91) near text ")"; expecting "<=", or "="
Error (10170): Verilog HDL syntax error at sha256_pipes2.v(91) near text "+"; expecting "<=", or "="
Error (10170): Verilog HDL syntax error at sha256_pipes2.v(91) near text ";"; expecting "<=", or "="
Error (10170): Verilog HDL syntax error at sha256_pipes2.v(92) near text "["; expecting "}"
Error (10170): Verilog HDL syntax error at sha256_pipes2.v(92) near text "["; expecting "<=", or "="
Error (10170): Verilog HDL syntax error at sha256_pipes2.v(96) near text "["; expecting "}"
Error (10170): Verilog HDL syntax error at sha256_pipes2.v(98) near text "["; expecting "}"
Error (10112): Ignored design unit "sha256_pipe2_base" at sha256_pipes2.v(27) due to previous errors
Error (10112): Ignored design unit "sha256_pipe130" at sha256_pipes2.v(128) due to previous errors
Error (10112): Ignored design unit "sha256_pipe123" at sha256_pipes2.v(159) due to previous errors
Error (10112): Ignored design unit "sha256_pipe129" at sha256_pipes2.v(181) due to previous errors
<SNIP>
Error: Quartus II Analysis & Synthesis was unsuccessful. 15 errors, 1 warning
Error: Peak virtual memory: 273 megabytes
Error: Processing ended: Thu Jun 14 23:16:18 2012
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01
Error: Peak virtual memory: 273 megabytes
Error: Processing ended: Thu Jun 14 23:16:18 2012
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 17 errors, 1 warning
The defines are unmodified also:
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
`define E0(x) ( {{x}[1:0],{x}[31:2]} ^ {{x}[12:0],{x}[31:13]} ^ {{x}[21:0],{x}[31:22]} )
`define E1(x) ( {{x}[5:0],{x}[31:6]} ^ {{x}[10:0],{x}[31:11]} ^ {{x}[24:0],{x}[31:25]} )
`define CH(x,y,z) ( (z) ^ ((x) & ((y) ^ (z))) )
`define MAJ(x,y,z) ( ((x) & (y)) | ((z) & ((x) | (y))) )
`define S0(x) ( { {x}[6:4] ^ {x}[17:15], {{x}[3:0], {x}[31:7]} ^ {{x}[14:0],{x}[31:18]} ^ {x}[31:3] } )
`define S1(x) ( { {x}[16:7] ^ {x}[18:9], {{x}[6:0], {x}[31:17]} ^ {{x}[8:0],{x}[31:19]} ^ {x}[31:10] } )
Here's lines 89-98 that are offending quartus.
data15_p1 <= `S1( S[i-1].data[`IDX(15)] ); // 3
data15_p2 <= data15_p1; // 1
data15_p3 <= ( ( i == 1 ) ? `S1( S[i-1].data[`IDX(14)] ) : S[i-1].data15_p2 ) + S[i-1].data[`IDX(9)] + S[i-1].data[`IDX(0)]; // 3
data[`IDX(15)] <= `S0( data_buf[`IDX(1)] ) + data15_p3; // 4
state_buf <= S[i-1].state; // 2
t1 <= `CH( S[i-1].state[`IDX(4)], S[i-1].state[`IDX(5)], S[i-1].state[`IDX(6)] ) + `E1( S[i-1].state[`IDX(4)] ) + S[i-1].t1_p1; // 6
state[`IDX(0)] <= `MAJ( state_buf[`IDX(0)], state_buf[`IDX(1)], state_buf[`IDX(2)] ) + `E0( state_buf[`IDX(0)] ) + t1; // 7
