Why is Butterfly Labs so secretive?

[scrybe]

I did read it, but I feel it still to be wrong. The PCB design has not changed that is the easy part, they should in theory be able to take the ASCI and drop it on a single pcb..... So your telling me they are using a different PCB and a ASIC then the one they are going to release give me a break. The chips are built around the PCB if it be 1 chip or 10 chips, to not have them done by prototype would be a stupid. Why would you take a proto type chip and put it on a pcb design you do not intend on using? So whats to say the chip will work on the pcb you change to... kinda a gamble wouldn't you say?

Right now they get their boards assembled somewhere else, this assembly is likely to include adding the BFL ASIC to the board and passing certain tests. BFL has to but them in cases, attach some stuff to the boards, flash, package and ship.

They want to bring more of it in-house and change the flow to have the PCB's printed, populated, and assembled all in one place. But that is not the plan for the first batch since they don't want to try to learn to ride the bike DURING a motocross event.

[BitcoinINV]

I did read it, but I feel it still to be wrong. The PCB design has not changed that is the easy part, they should in theory be able to take the ASCI and drop it on a single pcb..... So your telling me they are using a different PCB and a ASIC then the one they are going to release give me a break. The chips are built around the PCB if it be 1 chip or 10 chips, to not have them done by prototype would be a stupid. Why would you take a proto type chip and put it on a pcb design you do not intend on using? So whats to say the chip will work on the pcb you change to... kinda a gamble wouldn't you say?

Not sure about this. For a product like this I would imagine that it is more likely for the PCBs to be built around the ASICs. They did say that the same ASIC will be used in the Jalapeno, Single(s) and Mini Rig.

If you look at computer motherboards, everything is designed around the CPU socket and chipset - not the other way round.

They do not build computers out of FPGA's, that is supposed to be the chip they design the pcb around.
http://kaisemi.com/index.php/home

0% NRE 90,000 USD or so delivers the first batch of chips. Then the price drops, they offer 0% NRE yes that right lol. All you pay for is the first order and they make your chips directly from the specs of your FPGA.

[scrybe]

I already have talked to my  attorney general..... Ask BFL if they talked to the Attorney Generals office see if they will be honest. I am not going to argue the fact with you.

Please try again, your English was incomprehensible in that middle section (no offense, I don't understand what you are trying to say)

If you have talked to your AG could you give a quick sum-up of their level of investigation/concern/followup?

Thanks

[BitcoinINV]

Ask BFL if they have talked to any Gov officials. I am not the spokes person lol

[Gatorhex]

Companies like Intel are selling products that are available in stores, people do not have to ask questions to find out whether their products work. just buy.

I seem to remember Pentium75 and Pentium90 couldn't add two floating point number together without crashing.

They do not build computers out of FPGA's

Many 8bit computers were FPGAs

[AndrewBUD]

Companies like Intel are selling products that are available in stores, people do not have to ask questions to find out whether their products work. just buy.

I seem to remember Pentium75 and Pentium90 couldn't add two floating point number together without crashing.

That's when AMD was the shit

[bitmar]

Companies like Intel are selling products that are available in stores, people do not have to ask questions to find out whether their products work. just buy.

I seem to remember Pentium75 and Pentium90 couldn't add two floating point number together without crashing.

I seem to remember Pentium 60 - had more bugs. What if the chip from the BFL will have bugs? No one has ever done ASICs at such a level as BFL, is a new technology.  They want to spend a few days only on  testing of their chips.
I found only a few ready-made ASIC to sha256:

http://www.heliontech.com/downloads/fast_hash_asic_datasheet.pdf#view=Fit
http://www.cast-inc.com/ip-cores/encryption/sha-256/index.html
Hardcopy HC210F48-C - ALTERA

All of these chips offer several % of performance which offer BFL.

[majorddf]

No one has ever done ASICs at such a level as BFL, is a new technology

I know it has been said before elsewhere, but ASICS are not new technology. Only their application to Bitcoin is new.

There are plenty of companies out there who will make you the desired chip if you have the bucks.

[bitmar]

No one has ever done ASICs at such a level as BFL, is a new technology

I know it has been said before elsewhere, but ASICS are not new technology. Only their application to Bitcoin is new.

There are plenty of companies out there who will make you the desired chip if you have the bucks.

ASIC is a very old technology, I know that. BFL offers us a great Performance chips (this is new technology - new level). Many companies have tried to make fast hash ASIC chips but that chips were similar or a bit higher performance than FPGA. Generally, ASICs are only slightly faster than FPGAs, more energy efficient and cheaper to produce, more expensive to design. Nobody produces ASICs to achieve several times better performance than FPGAs, there are other advantages.

[gmaxwell]

Nobody produces ASICs to achieve several times better performance than FPGAs, there are other advantages.

Gibberish.

[BitcoinINV]

Nobody produces ASICs to achieve several times better performance than FPGAs, there are other advantages.

Gibberish.

I agree they take out lots of stuff that draws resources from a FPGA that is not needed in a ASIC

[bitmar]

Nobody produces ASICs to achieve several times better performance than FPGAs, there are other advantages.

Gibberish.

I wrote - several times faster. ASIC may indeed be faster than FPGAs, but this is not so big difference. This is the difference of approximately to 100%, no  1000% and more.  BFL offers us about 500% faster ASIC than existing FPGA.

I found an old comparison table:

and newer:
http://www.heliontech.com/fast_hash.htm

[Miles Bennett Dyson]

BFL Newsletter:

http://us6.campaign-archive2.com/?u=5015fc3486176144c53751877&id=ea153781b9&e=115fdfaa67

[vitruvio]

Nobody produces ASICs to achieve several times better performance than FPGAs, there are other advantages.

Gibberish.

I wrote - several times faster. ASIC may indeed be faster than FPGAs, but this is not so big difference. This is the difference of approximately to 100%, no  1000% and more.  BFL offers us about 500% faster ASIC than existing FPGA.

I found an old comparison table:

and newer:
http://www.heliontech.com/fast_hash.htm

This must be quite old, BFL talks about 1Ghz processor.

Regards

[mrb]

Nobody produces ASICs to achieve several times better performance than FPGAs, there are other advantages.

Gibberish.

I wrote - several times faster. ASIC may indeed be faster than FPGAs, but this is not so big difference. This is the difference of approximately to 100%, no  1000% and more.  BFL offers us about 500% faster ASIC than existing FPGA.

I found an old comparison table:

and newer:
http://www.heliontech.com/fast_hash.htm

What you need to understand is that this table does not show how many hashing cores can be placed on a chip.

The XC2V2000 for example only has 10 thousand slices. The table shows a SHA-256 core takes ~1000 slices and does ~1Gbps [16], so by putting 10 cores per FPGA the whole chip would do only ~10Gbps.

On the other hand, a 180nm ASIC of small size (50mm^2) has about 10 million gates. The table shows a SHA-256 core takes ~20 thousand gates and does ~2Gbps [21], so by putting 500 cores per ASIC the whole chip would do ~1000 Gbps.

Tada! There is your 100x difference. Roughly what BFL is promising (Single 832 Mhash/s vs. Single SC 60 Ghash/s.)

[PuertoLibre]

based on the power dissipation 90nm would be my guess.

I am going to take a blind guess...and say 65nm to 55nm. Though people say it is too expensive...this is what I imagine to be the case. Time will tell all tales...

[PuertoLibre]

Maybe its because BFL is worried they can't deliver on their promises.

They are secretive because they lack confidence in their abilities.

I think [speculation?] it is because they are having problems with their first batch which keeps increasing the delays and drawing the process out. Their window of opportunity keeps shrinking as BFL_Josh stated the issues keep eating through the padding of time they originally estimated their first deliveries.

Actually, they have pretty much said so in context of sourcing parts for their first batch. A competitor forced them to upgrade the hardware and everything that goes along with that. (Power/Heat issues apparently cropping up as well as parts sourcing issues)

They also briefly mentioned paying for expedited fabrication/shipping of the chips. (If I recall correctly)

There is a story that remains half-told as to why they would have to shell out the extra cash for that. I am not out to seed doubt, it just means like any other company they have issues that should be resolved with any new creation. It is expected.

[PuertoLibre]

maybe they are afraid of competition

so they dont want to disclose anything

100% correct... They wouldn't be spending so much on advertising if this wasn't the case.

I'll have to agree. I am thinking along the same lines.

[PuertoLibre]

Nobody produces ASICs to achieve several times better performance than FPGAs, there are other advantages.

Gibberish.

I wrote - several times faster. ASIC may indeed be faster than FPGAs, but this is not so big difference. This is the difference of approximately to 100%, no  1000% and more.  BFL offers us about 500% faster ASIC than existing FPGA.

I found an old comparison table:

and newer:
http://www.heliontech.com/fast_hash.htm

What you need to understand is that this table does not show how many hashing cores can be placed on a chip.

The XC2V2000 for example only has 10 thousand slices. The table shows a SHA-256 core takes ~1000 slices and does ~1Gbps [16], so by putting 10 cores per FPGA the whole chip would do only ~10Gbps.

On the other hand, a 180nm ASIC of small size (50mm^2) has about 10 million gates. The table shows a SHA-256 core takes ~20 thousand gates and does ~2Gbps [21], so by putting 500 cores per ASIC the whole chip would do ~1000 Gbps.

Tada! There is your 100x difference. Roughly what BFL is promising (Single 832 Mhash/s vs. Single SC 60 Ghash/s.)

+1
Insightful

Very few (including BFL) are talking about how many hashing units they have in each chip. Understandably so...

[squeept]

I demand to know what color socks each employee wears. Until I have photos of each employee's foot next to a driver's license, I will assume that BFL is a scam.