Process-invariant hardware metric: hash-meters per second (η-factor)

[gmaxwell]

And how would a consumer buying ASIC based product use this metric for choosing which product to buy?

You wouldn't— perhaps you've confused this for a thread in a marketplace section? Products are part of the subject of this subforum, but they're not the only part.

This is a technology thread, not a what to buy thread. You'll note that there is no mention of prices in the original post: any what-to-buy thread would be useless with them.

There are only 2 metric that are useful:
1) Cost in $/GH for manufacturer to make - only few know what it is exactly and can vary by 200%-500%
2) Cost in $/GH for consumer to buy

Ha. On the contrary, I think both of those metrics are irrelevant. What matters— when it comes to buying mining products at this time— is what is available when. ... but all three of these are offtopic for _this thread_. Please keep further discussion here to the subject of set out in the first post.

[GalaxyASIC]

And how would a consumer buying ASIC based product use this metric for choosing which product to buy?

You wouldn't— perhaps you've confused this for a thread in a marketplace section? Products are part of the subject of this subforum, but they're not the only part.

This is a technology thread, not a what to buy thread. You'll note that there is no mention of prices in the original post: any what-to-buy thread would be useless with them.

There are only 2 metric that are useful:
1) Cost in $/GH for manufacturer to make - only few know what it is exactly and can vary by 200%-500%
2) Cost in $/GH for consumer to buy

Ha. On the contrary, I think both of those metrics are irrelevant. What matters— when it comes to buying mining products at this time— is what is available when. ... but all three of these are offtopic for _this thread_. Please keep further discussion here to the subject of set out in the first post.

Obviously price goes hand in hand with availability.
But you still didn't answered how is this (hash-meters per second (η-factor)) useful to anyone?

[Inspector 2211]

EldenTyrell, on the website Bitfurystrikesback.com Mr. Bitfury claims a hash rate of 2.7 GH/s per chip. In this thread, you claim 2.0 GH/s per chip. Please explain and/or correct this discrepancy. Thank you.

[runeks]

Maybe it's just me, but when you tell me Bitfury has a 2800 score and KNC a score of 90, that really seems odd. Especially considering KNC's gigahash/watt is better than Bitfury's or BFL's. It really makes me question the relevance of this metric to me. Are you saying KNC, or someone, if they had access to KNC's design could replace it with a design that's 30 times more efficient? Are we saying KNC's design is basically one giant fuckup? Doesn't seem to make sense or accord with known facts.

I'm gonna assume that we simply just don't have enough technical details to make a determination and that's why KNC still hasn't been added to the OP list.

The highlighted part is incorrect. At least based on the announced specs for the KNC chip.

The power usage of the Bitfury chip is around 1 GH/J: https://bitcointalk.org/index.php?topic=228677.msg2635052#msg2635052

The power usage of the KNC chip is 400 Mhash/J: https://www.kncminer.com/categories/miners

[ujka]

EldenTyrell, on the website Bitfurystrikesback.com Mr. Bitfury claims a hash rate of 2.7 GH/s per chip. In this thread, you claim 2.0 GH/s per chip. Please explain and/or correct this discrepancy. Thank you.

They did some tests at 2.7 GH/s, but probably chip wasn't stable - even their 25 GH/s boad uses 16 chips!

[ujka]

Collecting data for CPU comparison takes time, there are so many models.
In the meantime, I put together a table calculating how many GH/s can be put on a wafer with chips we know:

wafer (mm)    chip       process (nm)     die(mm^2)   chip GH/s     dpw       wafer GH/s
----------------------------------------------------------------------------------------
300           avalon         110            16,13         0,282     4214      1188,35
300           bitfury         55            14,44         2         4717      9434,00
300           bfl             65            56,25         4         1167      4668,00
300           KnC             28          3025,00       100           11      1100,00

EDIT: KnC die size is not known. In the early stage of the KnC website, I remember reading die size of 55x55mm. On the 'openday', they were talking about package size of 70x70mm or more. Latest info on website is for 55x55mm package size.

[runeks]

How do you calculate that, exactly?

Is it simply wafer_area/die_area*GH_per_chip? When I try that my numbers don't quite match up with yours (although they're close).

Also, what is the figure for ASICMINER's chips?

[ujka]

'dpw' (die count estimation) is calculated by the formula (http://en.wikipedia.org/wiki/Wafer_(electronics)#Analytical_die_count_estimation):

dwp = PI * wafer_diammeter * (wafer_diammeter/(4*die_size) - 1/sqrt(2*die_size))

Don't know the exact die size for ASICMiner chip - is it 17,5 or 21,7 mm^2?
17,5: dwp = 3877, GH/s per wafer = 1291,04
21,7: dwp = 3112, GH/s per wafer = 1036,30

(over here, we are using ',' for 'decimal point')

[runeks]

'dpw' (die count estimation) is calculated by the formula (http://en.wikipedia.org/wiki/Wafer_(electronics)#Analytical_die_count_estimation):

dwp = PI * wafer_diammeter * (wafer_diammeter/(4*die_size) - 1/sqrt(2*die_size))

Don't know the exact die size for ASICMiner chip - is it 17,5 or 21,7 mm^2?
17,5: dwp = 3877, GH/s per wafer = 1291,04
21,7: dwp = 3112, GH/s per wafer = 1036,30

(over here, we are using ',' for 'decimal point')

Cool, thanks. I don't think ASICMINER has published the die size of their chip. We only have estimates. But it's probably in that area, perhaps even smaller.

[Bicknellski]

Ujka, bitfurry?

[ujka]

In prev. (erased) post I hardly noticed that strike over 'r'! Now I see 

[k9quaint]

Collecting data for CPU comparison takes time, there are so many models.
In the meantime, I put together a table calculating how many GH/s can be put on a wafer with chips we know:

wafer (mm)    chip       process (nm)     die(mm^2)   chip GH/s     dpw       wafer GH/s
----------------------------------------------------------------------------------------
300           avalon         110            16,13         0,282     4214      1188,35
300           bitfury         55            14,44         2         4717      9434,00
300           bfl             65            56,25         4         1167      4668,00
300           KnC             28          3025,00       100           11      1100,00

You put the package size instead of KNC's die size (which is currently unknown I think).

Our ASIC package selection has been optimized, allowing the use of a smaller package. The selected package is a 55mm x 55mm HFCBGA package (2046 ball count), optimized for maximum thermal characteristics.

https://www.kncminer.com/news/news-22

[RHA]

Yes, I must had misunderstood the video when I had been watching it for first time. There they stated quite clearly, the chip (the package) would be the size shown, about 60 mm x 60  mm,
not the die, which will be much smaller.
The conclusion:  η should be significantly greater than 90, and  η' quite higher than 6.5.

[Anenome5]

We've got info on KNC's die size and the like, how about an update to the OP?

[k9quaint]

We've got info on KNC's die size and the like, how about an update to the OP?

That has the package size, not the die size. Or if it does, I did not see it.

[ujka]

Od the package, there is also a die rectangle shown - 43 x 43mm, quad core (multi-chip package). Then each die is 21 x 21mm.

[eldentyrell]

I apologize for not responding over the last few days; catching up now….

[eldentyrell]

Not to add to the table yet, until the chip is working.

Thanks RHA, I appreciate you collecting this data and putting it in table form.  Please let me know when the vendor confirms these numbers (hopefully in something other than a video…) and gives a ship date so we have know when we can reasonably expect third-party verification.

KnC's chips don't stand well here. They just took some fpga desing, converted it to asic with some manufacturer's standard technique, and are going to put as many cores on a die as they can.

I can't comment on KnC's specific case, but this sort of situation is exactly what the eta-factor is designed to detect -- crappy designs which have simply had gobs of money thrown at them in the form of super-expensive masksets.  Products like that do not have much of a future, but you can fool investors with them for a while...

[eldentyrell]

Can we try to figure out this metric for the Block Erupter chips? I can't find the die area

Unfortunately we absolutely need the die area… there's no way around that.

[eldentyrell]

It seems the current formula attaches too much importance to the process node (the path width). I think it should be counted with power of 2 not 3.

No, it shouldn't… please re-read the original posting.  The feature size is counted to a power of 3 to account for reduction in area (factor of two) and the decrease in gate delay due to decreased channel length (an additional factor of one).  Please provide some sort of justification, other than:

(The path height is not directly proportional to its width - I think it can even be comparable between the processes in range 28-130 nm. I've found no exact info. I someone knows more, let us know.)

What the heck is the "path height"?  Are you talking about the channel oxide thickness?  That decreases too.  Either way, since silicon is dirt cheap the goal here is not to estimate the cost of the physical silicon required as a bulk material -- nobody cares about that.