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Author Topic: OpenCore has a open-soruce SHA core...  (Read 3327 times)
em3rgentOrdr
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September 23, 2010, 08:07:48 PM
 #1

I was browsing OpenCores.org and saw that they have an open-source GPL SHA crypto cores:

Quote
Description

This is a collection of SHA(Secure Hash Algorithm) cores. These include SHA-1, SHA-2 algorithms.
These cores are non-pipelined version of SHA, and have simple interfaces with the host side.

Overview
  • Category: Crypto core
  • Language: Verilog
  • Development status: Beta
  • Additional info: Design done
  • WishBone Compliant: No
  • License: LGPL

Features
  • Support SHA-1(160), SHA-2(256/384/512)
  • Use a simple 32-bit I/O bus interface
  • High performance
  • Share hardware between different SHA processing
  • Can operate up to 200MHz at 0.18um Standard cell design
  • Written in VerilogHDL

You can download it here.  I'm thinking that it would be cool if someone put this on an FPGA (or even fabricated it) and have it set to constantly generate SHA hashes to find bitcoins Smiley.  Probably wouldn't be as fast as a TESLA running CUDA bitcoin generation, but the idea of having a dedicated bitcoin generator piece of hardware sounded cool to me Smiley.

Anyone have an FPGA and want to try this out?

(update: here's another free crypto core - Nugroho Free Hash Cores (NFHC) currently support SHA-1, SHA-256, SHA-512 from FIPS-180 standard.)

"We will not find a solution to political problems in cryptography, but we can win a major battle in the arms race and gain a new territory of freedom for several years.

Governments are good at cutting off the heads of a centrally controlled networks, but pure P2P networks are holding their own."
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nelisky
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September 23, 2010, 08:12:46 PM
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I've been meaning to dive into FPGAs for too long now... if there are no takers that have both the hardware and the time/inclination, I can be bribed into doing this in exchange for a dev board donation Smiley

I'm just saying...

In fact, this could be the start of a company selling bitcoin generators Wink
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September 23, 2010, 09:06:38 PM
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Problem for me is, I've got the hardware and software(got it to try this) but haven't been good enough with VHDL to figure out how to interface it between that and Bitcoin.
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September 23, 2010, 09:13:54 PM
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Problem for me is, I've got the hardware and software(got it to try this) but haven't been good enough with VHDL to figure out how to interface it between that and Bitcoin.

hmmm, for testing I would probably get a UART core and feed the half baked hash, the initial nonce and the 256bit min hash value. It would do one set of parallel hash calculations for incrementing nonces and return the nonce with the lowest hash. This would make interfacing with bitcoin pretty easy, especially after svn r154.
em3rgentOrdr
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September 24, 2010, 09:10:07 AM
 #5

I don't have an FPGA, or else I would do it myself...I'd like to see what type of results other people get...

On a related note, the recently released (Sept 20, 2010) Sparc T3 chip has 16 cores, each with a hardware cryptographic accelerator and 8 hardware threads per core...  I'm wondering how many Hashes/Sec you could get out of a T3 Server Smiley.  (on another related note, it is too bad that since Oracle bought Sun, now all their stuff is closed-source...the Sparc T1 and T2 were open-sourced GPL...)

"We will not find a solution to political problems in cryptography, but we can win a major battle in the arms race and gain a new territory of freedom for several years.

Governments are good at cutting off the heads of a centrally controlled networks, but pure P2P networks are holding their own."
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September 24, 2010, 08:47:25 PM
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*&^%$# Oracle Lips sealed

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Cdecker
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September 28, 2010, 11:02:33 AM
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*&^%$# Oracle Lips sealed
+1

Want to see what developers are chatting about? http://bitcoinstats.com/irc/bitcoin-dev/logs/
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