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Author Topic: bASIC graphic renders and diagram  (Read 8422 times)
HDSolar
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December 11, 2012, 01:56:45 PM
 #21

Here's design of BTCFPGA custom-ASIC:


Pretty cool, isn't?!  Grin
So where can I order your design and when do you say your going to ship?  I hope you say December, HA, LOL  Love this post.....

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December 11, 2012, 07:23:01 PM
 #22

Yeah they could be prettier, but it's nice to see movement. As to the molex issue, I believe bASIC is moving toward a PCIe connector as a single molex would be pretty close to maxed current wise. This is a good choice IMO and the barrel connector is another option for powering the unit.

The design is very compact and efficient IMO, though it could obviously change significantly prior to shipping.

You an I are looking at different pictures, clearly.
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December 11, 2012, 07:31:39 PM
 #23

Clearly. Smiley

Last spec update I saw had board size at 7"x7.5"x2.167" for 72Gh. Given that we're talking about 16 90nm ASICs on that board I believe that to be very reasonable, but YMMV.

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December 11, 2012, 07:40:19 PM
 #24

If true to render, this would be the first ASIC (of any kind, bitcoin related or otherwise) I've ever seen that had JTAG.
At least one structured ASIC manufacturer I've seen actually requires JTAG for their own internal testing purposes, believe it or not. Besides, even if you're not planning on using it to test the chips themselves, you can always use the boundary scan chain to test the interconnects on the PCB they're mounted to.

Unless everything is on the chips, is this design not missing some stuff?
Yeah, it appears to be missing a few minor things like buck converters to actually power the chips. Nothing terribly important Wink

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December 11, 2012, 07:42:45 PM
 #25

Here's design of BTCFPGA custom-ASIC:


Pretty cool, isn't?!  Grin
So where can I order your design and when do you say your going to ship?  I hope you say December, HA, LOL  Love this post.....


Nice design..

Curious why the chips are different sizes in the drawing?



(not serious) Smiley


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crazyates
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December 11, 2012, 07:58:20 PM
 #26

Here's design of BTCFPGA custom-ASIC:


Pretty cool, isn't?!  Grin
I don't see any difference between your schematics (I just love that word) and the renderings in the OP. You better be careful or Tom will sue your ass for copyright infringement or something like that!

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AndrewBUD
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December 11, 2012, 08:19:59 PM
 #27

I'm going to fire up "Paint" and build my own asic device Cheesy


Mine will be circular.. "patent pending"


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December 11, 2012, 09:23:06 PM
 #28

Responses like this are exactly why Tom didnt feel comfortable posting pictures of the prototype, or power figures (even a guess), or a rendering. You cant please everyone and there will always be someone who bitches. I agree that they could be better, but I would rather devote time into the physical product rather than making fancy renderings and pictures to plaster all over net.

Yeah they could be prettier, but it's nice to see movement. As to the molex issue, I believe bASIC is moving toward a PCIe connector as a single molex would be pretty close to maxed current wise. This is a good choice IMO and the barrel connector is another option for powering the unit.

The design is very compact and efficient IMO, though it could obviously change significantly prior to shipping.

You an I are looking at different pictures, clearly.

If you look at the MMQs vs BFL singles, the MMQ had a lot less board components than the singles did/do. Not saying that the bASIC will be the same way but the MMQs worked just fine....

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December 11, 2012, 09:37:38 PM
 #29

Responses like this are exactly why Tom didnt feel comfortable posting pictures of the prototype, or power figures (even a guess), or a rendering. You cant please everyone and there will always be someone who bitches. I agree that they could be better, but I would rather devote time into the physical product rather than making fancy renderings and pictures to plaster all over net.

Yeah they could be prettier, but it's nice to see movement. As to the molex issue, I believe bASIC is moving toward a PCIe connector as a single molex would be pretty close to maxed current wise. This is a good choice IMO and the barrel connector is another option for powering the unit.

The design is very compact and efficient IMO, though it could obviously change significantly prior to shipping.

You an I are looking at different pictures, clearly.

If you look at the MMQs vs BFL singles, the MMQ had a lot less board components than the singles did/do. Not saying that the bASIC will be the same way but the MMQs worked just fine....

If I had to guess, I'd say they might use something like the Delta POL convertor that they used on the MMQ.
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December 11, 2012, 09:37:50 PM
 #30

Pretty sweet looking. I probably would have gone with one big fan rather than four small ones for noise but I'm sure it will be easy enough to change.

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December 11, 2012, 09:38:35 PM
 #31

No fans. Water!

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December 11, 2012, 09:48:43 PM
 #32

Pretty sweet looking. I probably would have gone with one big fan rather than four small ones for noise but I'm sure it will be easy enough to change.

If the chips are numbered like this:

 1  2  3  4
 5  6  7  8
 9 10 11 12
13 14 15 16

One large fan probably wouldn't cool chips 6,7,10, and 11 (the chips in the center) all that well. 4 small fans helps keep equal cooling across all chips. It's still not perfect, but decent.

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December 11, 2012, 09:53:02 PM
 #33

Pretty sweet looking. I probably would have gone with one big fan rather than four small ones for noise but I'm sure it will be easy enough to change.

If the chips are numbered like this:

 1  2  3  4
 5  6  7  8
 9 10 11 12
13 14 15 16

One large fan probably wouldn't cool chips 6,7,10, and 11 (the chips in the center) all that well. 4 small fans helps keep equal cooling across all chips. It's still not perfect, but decent.
Also realised the board is 7 1/2 inches by 7 inches! That's huge fan.

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December 11, 2012, 09:54:48 PM
 #34

Pretty sweet looking. I probably would have gone with one big fan rather than four small ones for noise but I'm sure it will be easy enough to change.

If the chips are numbered like this:

 1  2  3  4
 5  6  7  8
 9 10 11 12
13 14 15 16

One large fan probably wouldn't cool chips 6,7,10, and 11 (the chips in the center) all that well. 4 small fans helps keep equal cooling across all chips. It's still not perfect, but decent.

Would it even need a fan at all? Say its 120watts and 16 chips, thats 7.5watts per chip. Wouldnt a heatsink alone be enough to keep them cool?

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December 11, 2012, 09:56:02 PM
 #35

180mm = 7.087 inches. Now that's a cooling fan.

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December 11, 2012, 09:59:07 PM
 #36

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December 11, 2012, 10:04:34 PM
 #37

Clearly. Smiley

Last spec update I saw had board size at 7"x7.5"x2.167" for 72Gh. Given that we're talking about 16 90nm ASICs on that board I believe that to be very reasonable, but YMMV.

7" x 7.5" you say?

Yes, that's so compact!

and so obviously efficient!
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December 11, 2012, 10:13:45 PM
 #38

Clearly. Smiley

Last spec update I saw had board size at 7"x7.5"x2.167" for 72Gh. Given that we're talking about 16 90nm ASICs on that board I believe that to be very reasonable, but YMMV.

7" x 7.5" you say?

Yes, that's so compact!

and so obviously efficient!

I'm glad we agree on this. Wink

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December 11, 2012, 10:14:23 PM
 #39

180mm = 7.087 inches. Now that's a cooling fan.
The fans don't seems to extend the full 7", so I'm going to assume that maybe it's 4x 70mm or 80mm fans? I'm assuming you could replace them with a larger 140mm fan, but like I said, it wouldn't cool the center ones as well.

Would it even need a fan at all? Say its 120watts and 16 chips, thats 7.5watts per chip. Wouldnt a heatsink alone be enough to keep them cool?
Consider it this way: the current MMQ has 4 chips, and pulls 40W. Even at 10W/each, they have a heatsink with a built in fan for every chip. Lowering the thermal output by 25%, but then sharing one larger fan between 4 heatsinks, would be about the same.

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December 11, 2012, 10:34:45 PM
 #40

Quote
The diameter of the circular part of the fan unit measures 78mm.

https://www.btcfpga.com/forum/index.php?topic=355.15

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