The State of the ASIC Market

[rchapoteau]

Maybe I'm missing something, but what is the countdown timer to if it isn't the ship date?  Is that when things are supposed to be shown off?

Personally I don't care about one company Vs another in a he said she said game.  It's all just words until someone can actually show a working product, and I think that is all anyone cares about.

[1715316628]

1715316628

[repentance]

Maybe I'm missing something, but what is the countdown timer to if it isn't the ship date?  Is that when things are supposed to be shown off?

The countdown timer is for when they ship the first units.  It says "ships in" directly above the timer.

As I understand it, all 300 units won't be shipped tonight.

...our conservative estimate on our shipping capacity is 300 units in two weeks...

http://support.avalon-asic.com/solution/categories/40996/folders/66201/articles/31066-when-are-the-avalon-asics-shipping-

This post from BitSyncom earlier today regarding shipping options also suggests that not all units will be shipped tonight.

correct, I am making form for people to choose right now, should be ready in a few hours.

https://bitcointalk.org/index.php?topic=120184.msg1464530#msg1464530

If you're going to export 300 units at once, you don't leave sorting out shipping preferences until the day of shipment - the paperwork's too much of a pain in the ass to do it at the last moment.

[ChipGeek]

It is important to know that is not possible to switch packaging after you have tape-out the chip.

This is both true and false depending on how you interpret it.

It is true because you cannot (reasonably or easily) use silicon designed for a QFN package (with edge bond wires) for a flip-chip BGA package (with an array of balls on the silicon similar to a tiny BGA).

It is false because the following scenario is possible.  We do something very similar with some of our chips.
1) Tape-out all layers to the fab.
2) The fab starts the N-week process with the bottom layers.
3) We realize we have a bug (or BFL decides to switch from QFN to FCBGA)
4) We make the changes to the top layer(s) of metal and tape-out only these top layer(s)
(Note that the wafers are not yet at the step where the top layers are done.)
5) The fab charges us a boatload of money for new top layer masks and they use these new masks when the wafers get to that step.

My best GUESS as to the events of BFL's silicon are that they actually got some engineering samples of their chips in a QFN package back in November or December and realized they generated too much heat for that package and melted some.  So they made the changes to the mask set and did another tape-out for these changes.  If the fab was already past this step, a fresh batch of wafers would need to be started (and the old ones scrapped).  If you assume BFL is genuine in delivering an ASIC product ASAP, then their delay stories are consistent with the above.

It does appear to me that the public chip photo is one of a wire bond (QFN package) design, not a FCBGA design.  Unless there is a new photo out (I've been away from the forums for 1.5 weeks or so).

Disclaimers:
I ordered 1 BFL SC single.  All I have so far is an email receipt but I believe I will get my SC very soon.
I ordered 1 bASIC and now have my refund - which I will likely re-invest in another BFL SC or an Avalon.
I do not work for any bitcoin ASIC company and have no "insider knowledge" of them beyond what is posted on the public forums.
I do work for a non-bitcoin ASIC company and have been working in this industry for over 25 years.  (I started with a 2 micron = 2000nm process!  )

[MrTeal]

It is important to know that is not possible to switch packaging after you have tape-out the chip.

This is both true and false depending on how you interpret it.

It is true because you cannot (reasonably or easily) use silicon designed for a QFN package (with edge bond wires) for a flip-chip BGA package (with an array of balls on the silicon similar to a tiny BGA).

It is false because the following scenario is possible.  We do something very similar with some of our chips.
1) Tape-out all layers to the fab.
2) The fab starts the N-week process with the bottom layers.
3) We realize we have a bug (or BFL decides to switch from QFN to FCBGA)
4) We make the changes to the top layer(s) of metal and tape-out only these top layer(s)
(Note that the wafers are not yet at the step where the top layers are done.)
5) The fab charges us a boatload of money for new top layer masks and they use these new masks when the wafers get to that step.

My best GUESS as to the events of BFL's silicon are that they actually got some engineering samples of their chips in a QFN package back in November or December and realized they generated too much heat for that package and melted some.  So they made the changes to the mask set and did another tape-out for these changes.  If the fab was already past this step, a fresh batch of wafers would need to be started (and the old ones scrapped).  If you assume BFL is genuine in delivering an ASIC product ASAP, then their delay stories are consistent with the above.

It does appear to me that the public chip photo is one of a wire bond (QFN package) design, not a FCBGA design.  Unless there is a new photo out (I've been away from the forums for 1.5 weeks or so).

Disclaimers:
I ordered 1 BFL SC single.  All I have so far is an email receipt but I believe I will get my SC very soon.
I ordered 1 bASIC and now have my refund - which I will likely re-invest in another BFL SC or an Avalon.
I do not work for any bitcoin ASIC company and have no "insider knowledge" of them beyond what is posted on the public forums.
I do work for a non-bitcoin ASIC company and have been working in this industry for over 25 years.  (I started with a 2 micron = 2000nm process!  )

I've suggested the same scenario on the BFL forums, and Josh has that while he's not sure on the specifics of the change, that is likely.