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Author Topic: ASIC architectures?  (Read 867 times)
kingcoin
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March 19, 2013, 03:58:20 PM
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Are the architectures of some of the current ASIC offerings described anywhere?

  • How many SHA256 cores do they typically have per die?
  • At what frequency or throughput do the cores operate?
  • What kind of external interface do they have?
  • What kind of chip to chip interconnect do they have?
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March 20, 2013, 03:56:57 AM
 #2

Briefly, without looking it up I can tell you for BFL:

16 engines/chip, just under 500MHz, USB only. No idea about interconnect.

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