QuintLeo
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Activity: 1498
Merit: 1030
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October 18, 2016, 03:40:41 AM |
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Has anyone tried the "bypass the fan pwm control line to give constant 100%" trick?
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I'm no longer legendary just in my own mind!
Like something I said? Donations gratefully accepted. LYLnTKvLefz9izJFUvEGQEZzSkz34b3N6U (Litecoin)
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Xircom
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Activity: 938
Merit: 1000
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October 18, 2016, 09:17:51 PM |
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According to Bitmain support, this firmware is for all S9`s. look at the description of the file: Antminer-S9-all-201610180851-autofreq-user.tar Be very careful updating your S9`s some of mine went mental in chip temp and I had to flash with older bios, something is very wrong with this bios.  |
BTC: 1MyJmxS9ER5ZBNvpG3LhoUXGotpzbPowed
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Ninetoe
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Activity: 45
Merit: 0
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October 18, 2016, 09:36:37 PM
Last edit: October 18, 2016, 10:15:36 PM by Ninetoe |
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stupid as i am i did the firmware upgrade and this is all that happens now. PS: its been like this for hours, ive done a few reboots too, and factory reset etc. http://i63.tinypic.com/2ez1vh1.pngBooting Linux on physical CPU 0x0
Initializing cgroup subsys cpuset
Linux version 3.10.31-ltsi-00003-gcf03eb9 (lzq@armdev01) (gcc version 4.7.3 20121106 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2012.11-20121123 - Linaro GCC 2012.11) ) #81 SMP Mon Apr 25 11:20:36 CST 2016
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: Altera SOCFPGA, model: Altera SOCFPGA Cyclone V
Memory policy: ECC disabled, Data cache writealloc
On node 0 totalpages: 258048
free_area_init_node: node 0, pgdat 806e5cc0, node_mem_map 8072a000
Normal zone: 2016 pages used for memmap
Normal zone: 0 pages reserved
Normal zone: 258048 pages, LIFO batch:31
PERCPU: Embedded 8 pages/cpu @80f17000 s11200 r8192 d13376 u32768
pcpu-alloc: s11200 r8192 d13376 u32768 alloc=8*4096
pcpu-alloc: [0] 0 [0] 1
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 256032
Kernel command line: mem=1008M console=ttyS0,115200 root=/dev/mtdblock3 rw rootfstype=jffs2
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 1008MB = 1008MB total
Memory: 1015844k/1015844k available, 16348k reserved, 0K highmem
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
vmalloc : 0xbf800000 - 0xff000000 (1016 MB)
lowmem : 0x80000000 - 0xbf000000 (1008 MB)
modules : 0x7f000000 - 0x80000000 ( 16 MB)
.text : 0x80008000 - 0x8065a930 (6475 kB)
.init : 0x8065b000 - 0x806adbc0 ( 331 kB)
.data : 0x806ae000 - 0x806e9990 ( 239 kB)
.bss : 0x806e9990 - 0x80729384 ( 255 kB)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
Hierarchical RCU implementation.
NR_IRQS:16 nr_irqs:16 16
sched_clock: 32 bits at 100MHz, resolution 10ns, wraps every 42949ms
Console: colour dummy device 80x30
Calibrating delay loop... 1196.85 BogoMIPS (lpj=5984256)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
ftrace: allocating 17687 entries in 52 pages
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x804ab220 - 0x804ab278
CPU1: failed to come online
Brought up 1 CPUs
SMP: Total of 1 processors activated (1196.85 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
NET: Registered protocol family 16
fpga bridge driver
DMA: preallocated 256 KiB pool for atomic coherent allocations
L310 cache controller enabled
l2x0: 8 ways, CACHE_ID 0x410030c9, AUX_CTRL 0x32460000, Cache size: 524288 B
syscon fffef000.l2-cache: regmap [mem 0xfffef000-0xfffeffff] registered
syscon ffd05000.rstmgr: regmap [mem 0xffd05000-0xffd05fff] registered
syscon ffc25000.sdrctl: regmap [mem 0xffc25000-0xffc25fff] registered
syscon ff800000.l3regs: regmap [mem 0xff800000-0xff800fff] registered
syscon ffd08000.sysmgr: regmap [mem 0xffd08000-0xffd0bfff] registered
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
altera_hps2fpga_bridge fpgabridge.2: fpga bridge [hps2fpga] registered as device hps2fpga
altera_hps2fpga_bridge fpgabridge.2: init-val not specified
altera_hps2fpga_bridge fpgabridge.3: fpga bridge [lshps2fpga] registered as device lwhps2fpga
altera_hps2fpga_bridge fpgabridge.3: init-val not specified
altera_hps2fpga_bridge fpgabridge.4: fpga bridge [fpga2hps] registered as device fpga2hps
altera_hps2fpga_bridge fpgabridge.4: init-val not specified
bio: create slab <bio-0> at 0
FPGA Mangager framework driver
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
Switching to clocksource timer0
NET: Registered protocol family 2
TCP established hash table entries: 8192 (order: 4, 65536 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
TCP: reno registered
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
arm-pmu arm-pmu: PMU:CTI successfully enabled for 1 cores
NFS: Registering the id_resolver key type
Key type id_resolver registered
Key type id_legacy registered
NTFS driver 2.1.30 [Flags: R/W].
jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
msgmni has been set to 1984
io scheduler noop registered (default)
Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
ffc02000.serial0: ttyS0 at MMIO 0xffc02000 (irq = 194) is a 16550A
console [ttyS0] enabled
altera_fpga_manager ff706000.fpgamgr: fpga manager [Altera FPGA Manager] registered as minor 0
brd: module loaded
denali-nand-dt ff900000.nand: Dump timing register values:acc_clks: 4, re_2_we: 20, re_2_re: 20
we_2_re: 12, addr_2_data: 14, rdwr_en_lo_cnt: 2
rdwr_en_hi_cnt: 2, cs_setup_cnt: 2
ONFI param page 0 valid
ONFI flash detected
NAND device: Manufacturer ID: 0x2c, Chip ID: 0xda (Micron MT29F2G08ABAEAWP), 256MiB, page size: 2048, OOB size: 64
Bad block table found at page 131008, version 0x01
Bad block table found at page 130944, version 0x01
5 ofpart partitions found on MTD device denali-nand
Creating 5 MTD partitions on "denali-nand":
0x000000000000-0x000001000000 : "NAND Flash Boot Area 16MB"
0x000001000000-0x000002000000 : "NAND Flash Boot Area backup1 16MB"
0x000002000000-0x000003000000 : "NAND Flash Boot Area backup2 16MB"
0x000003000000-0x00000b000000 : "NAND Flash jffs2 Root Filesystem 128MB"
0x00000b000000-0x000010000000 : "NAND Flash jffs2 Root Filesystem 80MB"
dw_spi_mmio fff00000.spi: master is unqueued, this is deprecated
CAN device driver interface
c_can_platform ffc00000.d_can: invalid resource
c_can_platform ffc00000.d_can: control memory is not used for raminit
c_can_platform ffc00000.d_can: c_can_platform device registered (regs=bf8dc000, irq=163)
stmmac_hw_init: 1000M
stmmac - user ID: 0x10, Synopsys ID: 0x37
Ring mode enabled
DMA HW capability register supported
Enhanced/Alternate descriptors
Enabled extended descriptors
RX Checksum Offload Engine supported (type 2)
TX Checksum insertion supported
Enable RX Mitigation via HW Watchdog Timer
libphy: stmmac: probed
eth0: PHY ID 0007c0f1 at 0 IRQ POLL (stmmac-0:00) active
usbcore: registered new interface driver usb-storage
mousedev: PS/2 mouse device common for all mice
i2c /dev entries driver
Synopsys Designware Multimedia Card Interface Driver
dwmmc_socfpga ff704000.dwmmc0: couldn't determine pwr-en, assuming pwr-en = 0
dwmmc_socfpga ff704000.dwmmc0: Using internal DMA controller.
dwmmc_socfpga ff704000.dwmmc0: Version ID is 240a
dwmmc_socfpga ff704000.dwmmc0: DW MMC controller at irq 171, 32 bit host data width, 1024 deep fifo
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
dwmmc_socfpga ff704000.dwmmc0: 1 slots initialized
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
oprofile: using arm/armv7-ca9
TCP: cubic registered
NET: Registered protocol family 10
sit: IPv6 over IPv4 tunneling driver
NET: Registered protocol family 17
NET: Registered protocol family 15
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20120528 t)
can: netlink gateway (rev 20130117) max_hops=1
8021q: 802.1Q VLAN Support v1.8
Key type dns_resolver registered
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
ThumbEE CPU extension supported.
Registering SWP/SWPB emulation handler
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
jffs2: Empty flash at 0x01397ea4 ends at 0x01398000
VFS: Mounted root (jffs2 filesystem) on device 31:3.
devtmpfs: mounted
Freeing unused kernel memory: 328K (8065b000 - 806ad000)
eth0: device MAC address 56:d9:6b:09:dc:23
init phy ok
PHY DMA init OK
eth0: device MAC address 00:1d:6c:ed:31:bf
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
libphy: stmmac-0:00 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
In axi fpga driver!
Original value in RESET_MANAGER_BASE_ADDR + BRGMODRST_ADDR is 0x0
request_mem_region OK!
AXI fpga dev virtual address is 0xbf942000
*base_vir_addr = 0xc504
In fpga mem driver!
request_mem_region OK!
fpga mem virtual address is 0xc0000000
eth0: device MAC address 00:1d:6c:ed:31:bf
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
eth0: device MAC address 00:1d:6c:ed:31:bf
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
libphy: stmmac-0:00 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
prepare send works thread on chain[0]
prepare send works thread on chain[1]
prepare send works thread on chain[2]
prepare send works thread on chain[3]
prepare send works thread on chain[4]
prepare send works thread on chain[5]
prepare send works thread on chain[6]
prepare send works thread on chain[7]
prepare send works thread on chain[8]
prepare send works thread on chain[9]
prepare send works thread on chain[10]
prepare send works thread on chain[11]
prepare send works thread on chain[12]
prepare send works thread on chain[13]
prepare send works thread on chain[14]
prepare send works thread on chain[15]
Find hashboard on Chain[0]
Find hashboard on Chain[2]
Find hashboard on Chain[3]
chain[0] has no freq in PIC! Will use default freq=600 and jump over...
chain[2] has no freq in PIC! Will use default freq=600 and jump over...
chain[3] has no freq in PIC! Will use default freq=600 and jump over...
set command mode to VIL
singleBoardTest: AsicType = 1387
singleBoardTest: asicNum = 64
singleBoardTest: real AsicNum = 63
--- check asic number
set_baud=1
The min freq=700
set real timeout 52, need sleep=379392
disable_pic_dac on chain[0] testDone[0]=1
disable_pic_dac on chain[2] testDone[2]=1
disable_pic_dac on chain[3] testDone[3]=1
search freq for 1 times, completed chain = 3, total chain num = 3
restart Miner chance num=2
waiting for send_func to exit of chain[0]
waiting for send_func to exit of chain[1]
waiting for send_func to exit of chain[2]
waiting for send_func to exit of chain[3]
waiting for send_func to exit of chain[4]
waiting for send_func to exit of chain[5]
waiting for send_func to exit of chain[6]
waiting for send_func to exit of chain[7]
waiting for send_func to exit of chain[8]
waiting for send_func to exit of chain[9]
waiting for send_func to exit of chain[10]
waiting for send_func to exit of chain[11]
waiting for send_func to exit of chain[12]
waiting for send_func to exit of chain[13]
waiting for send_func to exit of chain[14]
waiting for send_func to exit of chain[15]
waiting for receive_func to exit!
waiting for pic heart to exit!
Start bmminer ...
Chain[J1] has no freq in PIC, set default freq=600M
Chain[J1] has no core num in PIC
Chain[J3] has no freq in PIC, set default freq=600M
Chain[J3] has no core num in PIC
Chain[J4] has no freq in PIC, set default freq=600M
Chain[J4] has no core num in PIC
read PIC voltage=897 on chain[0]
Chain:0 chipnum=63
Chain[J1] voltage added=0.0V
Chain[J1] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:0 temp offset=0
Chain:0 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:0 max freq=600
Chain:0 min freq=600
read PIC voltage=897 on chain[2]
Chain:2 chipnum=63
Chain[J3] voltage added=0.0V
Chain[J3] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:2 temp offset=0
Chain:2 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:2 max freq=600
Chain:2 min freq=600
read PIC voltage=897 on chain[3]
Chain:3 chipnum=62
Chain[J4] voltage added=0.0V
Chain[J4] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:3 temp offset=0
Chain:3 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600
Chain:3 max freq=600
Chain:3 min freq=600
Miner fix freq ...
read PIC voltage=897 on chain[0]
Chain:0 chipnum=63
Chain[J1] voltage added=0.0V
Chain[J1] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:0 temp offset=0
Chain:0 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:0 max freq=600
Chain:0 min freq=600
read PIC voltage=897 on chain[2]
Chain:2 chipnum=63
Chain[J3] voltage added=0.0V
Chain[J3] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:2 temp offset=0
Chain:2 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:2 max freq=600
Chain:2 min freq=600
read PIC voltage=897 on chain[3]
Chain:3 chipnum=62
Chain[J4] voltage added=0.0V
Chain[J4] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:3 temp offset=0
Chain:3 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600
Chain:3 max freq=600
Chain:3 min freq=600
max freq = 600
prepare send works thread on chain[0]
prepare send works thread on chain[1]
prepare send works thread on chain[2]
prepare send works thread on chain[3]
prepare send works thread on chain[4]
prepare send works thread on chain[5]
prepare send works thread on chain[6]
prepare send works thread on chain[7]
prepare send works thread on chain[8]
prepare send works thread on chain[9]
prepare send works thread on chain[10]
prepare send works thread on chain[11]
prepare send works thread on chain[12]
prepare send works thread on chain[13]
prepare send works thread on chain[14]
prepare send works thread on chain[15]
do 12 8xPatten test for 1 times
Find hashboard on Chain[0]
Find hashboard on Chain[2]
Find hashboard on Chain[3]
use PIC voltage=897 on chain[0]
now set pic voltage=79 on chain[0]
use PIC voltage=897 on chain[2]
now set pic voltage=79 on chain[2]
use PIC voltage=897 on chain[3]
now set pic voltage=79 on chain[3]
enable_pic_dac on chain[0]
enable_pic_dac on chain[2]
enable_pic_dac on chain[3]
set command mode to VIL
doHeatBoard: AsicType = 1387
doHeatBoard: asicNum = 64
doHeatBoard: real AsicNum = 63
--- check asic number
check chain[0]: asicNum = 63
check chain[2]: asicNum = 63
check chain[3]: asicNum = 62
Error: The AsicNum=62 on chain[3]!
Set Freq of PIC for Test Patten on Chain[0]
Set Freq of PIC for Test Patten on Chain[2]
Set Freq of PIC for Test Patten on Chain[3]
set_baud=1
anyone got a older firmware file for s9 b9 ? |
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NotFuzzyWarm (OP)
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Activity: 3822
Merit: 2706
Evil beware: We have waffles!
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October 19, 2016, 01:05:33 AM
Last edit: October 19, 2016, 02:34:20 AM by NotFuzzyWarm |
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Ouch!!!!
One trick I learned after munging a s9 Frimware: Unplug the PCI power to the hash boards and power only the controller.
Power up, wait several min and see if the Bitmain GUI reports life (socket connection error goes away).
If no go, still only with controller power, press the reset button for ~ 10sec then release it. Wait several more min to see if it lives. If it is alive you should be able to set pools, etc even without the hash boards working.
If it comes back to life, power down, reconnect power to hash boards and pray everything works....
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mindtrip
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October 19, 2016, 03:07:32 PM |
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So it would seem like upgrading to the latest FW on the website on old miners is not advisable right now is that the general agreement here?
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NotFuzzyWarm (OP)
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October 19, 2016, 03:47:22 PM
Last edit: October 19, 2016, 05:56:54 PM by NotFuzzyWarm |
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So it would seem like upgrading to the latest FW on the website on old miners is not advisable right now is that the general agreement here?
Grant you so far we have few data points but -- correct. For the old miners, if the original/older firmware works then I say do not upgrade. Most of my miners except the B1 (changed to low voltage version) are running the firmware they shipped with. As for applying the new firmware to the batch-16/17 miners, I am going to wait a bit to see any problems other folks have before *maybe* upgrading. |
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sidehack
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Curmudgeonly hardware guy
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October 19, 2016, 04:04:32 PM |
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I know most folks don't really take stuff apart, but can someone confirm whether or not the new-batch S9 boards have the U2 digital potentiometer populated? The ones I've looked at from older batches don't, and I haven't seen any adjustments in voltage during startup so I wonder if these aren't made for a fixed core voltage. The new ones look to be adjusting voltage on the fly, like S7 boards should have been capable of, so either they're doing something unexpected or that dpot should be on there.
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goxed
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Bitcoin / Crypto mining Hardware.
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October 19, 2016, 06:06:57 PM |
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I know most folks don't really take stuff apart, but can someone confirm whether or not the new-batch S9 boards have the U2 digital potentiometer populated? The ones I've looked at from older batches don't, and I haven't seen any adjustments in voltage during startup so I wonder if these aren't made for a fixed core voltage. The new ones look to be adjusting voltage on the fly, like S7 boards should have been capable of, so either they're doing something unexpected or that dpot should be on there.
Can you send a pic of the board and the part, so that it's easy to locate U2. Thanks |
Revewing Bitcoin / Crypto mining Hardware.
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sidehack
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October 19, 2016, 06:08:46 PM |
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Far as I can tell, the buck circuit is basically the same as the S7. U2 is the part replaced by a trimpot in the Cheap and Easy S7 Repair thread from a few months ago that has a bunch of pictures already.
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mindtrip
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October 19, 2016, 06:10:35 PM |
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So it would seem like upgrading to the latest FW on the website on old miners is not advisable right now is that the general agreement here?
Grant you so far we have few data points but -- correct. For the old miners, if the original/older firmware works then I say do not upgrade. Most of my miners except the B1 (changed to low voltage version) are running the firmware they shipped with. As for applying the new firmware to the batch-16/17 miners, I am going to wait a bit to see any problems other folks have before *maybe* upgrading. Ok so ill wait till the kinks in this FW transition process are resolved, my miners are pretty happy with the last stable FW most operating happy at higher clock speeds and very stable in a controlled data center so I think ill skip this update as I dont need added headaches right now |
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NotFuzzyWarm (OP)
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Evil beware: We have waffles!
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October 19, 2016, 06:10:38 PM |
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I know most folks don't really take stuff apart, but can someone confirm whether or not the new-batch S9 boards have the U2 digital potentiometer populated? The ones I've looked at from older batches don't, and I haven't seen any adjustments in voltage during startup so I wonder if these aren't made for a fixed core voltage. The new ones look to be adjusting voltage on the fly, like S7 boards should have been capable of, so either they're doing something unexpected or that dpot should be on there.
With the miner & fans running you kind of see the area where the U2 pads are but I couldn't really tell 'cause the fans blur things... Maybe a well-timed flash could catch it. A snippet from the kernel logs shows they definitely are doing something to control Vcore on-the-fly. use PIC voltage=870 on chain[5]
now set pic voltage=125 on chain[5]
use PIC voltage=870 on chain[6]
now set pic voltage=125 on chain[6]
use PIC voltage=870 on chain[7]
now set pic voltage=125 on chain[7]
enable_pic_dac on chain[5]
enable_pic_dac on chain[6]
enable_pic_dac on chain[7]
set command mode to VIL |
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goxed
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Bitcoin / Crypto mining Hardware.
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October 19, 2016, 06:41:54 PM |
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Revewing Bitcoin / Crypto mining Hardware.
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NotFuzzyWarm (OP)
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Activity: 3822
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Evil beware: We have waffles!
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October 19, 2016, 06:58:14 PM
Last edit: March 15, 2017, 11:47:23 PM by NotFuzzyWarm |
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Very cool.... looking through the index I see lots of v adjustment code. Now question is: does the PIC talk directly to the Vreg or to a DPOT? |
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SEGMining
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October 19, 2016, 08:12:48 PM |
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stupid as i am i did the firmware upgrade and this is all that happens now. PS: its been like this for hours, ive done a few reboots too, and factory reset etc.  Booting Linux on physical CPU 0x0
Initializing cgroup subsys cpuset
Linux version 3.10.31-ltsi-00003-gcf03eb9 (lzq@armdev01) (gcc version 4.7.3 20121106 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2012.11-20121123 - Linaro GCC 2012.11) ) #81 SMP Mon Apr 25 11:20:36 CST 2016
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: Altera SOCFPGA, model: Altera SOCFPGA Cyclone V
Memory policy: ECC disabled, Data cache writealloc
On node 0 totalpages: 258048
free_area_init_node: node 0, pgdat 806e5cc0, node_mem_map 8072a000
Normal zone: 2016 pages used for memmap
Normal zone: 0 pages reserved
Normal zone: 258048 pages, LIFO batch:31
PERCPU: Embedded 8 pages/cpu @80f17000 s11200 r8192 d13376 u32768
pcpu-alloc: s11200 r8192 d13376 u32768 alloc=8*4096
pcpu-alloc: [0] 0 [0] 1
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 256032
Kernel command line: mem=1008M console=ttyS0,115200 root=/dev/mtdblock3 rw rootfstype=jffs2
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 1008MB = 1008MB total
Memory: 1015844k/1015844k available, 16348k reserved, 0K highmem
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
vmalloc : 0xbf800000 - 0xff000000 (1016 MB)
lowmem : 0x80000000 - 0xbf000000 (1008 MB)
modules : 0x7f000000 - 0x80000000 ( 16 MB)
.text : 0x80008000 - 0x8065a930 (6475 kB)
.init : 0x8065b000 - 0x806adbc0 ( 331 kB)
.data : 0x806ae000 - 0x806e9990 ( 239 kB)
.bss : 0x806e9990 - 0x80729384 ( 255 kB)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
Hierarchical RCU implementation.
NR_IRQS:16 nr_irqs:16 16
sched_clock: 32 bits at 100MHz, resolution 10ns, wraps every 42949ms
Console: colour dummy device 80x30
Calibrating delay loop... 1196.85 BogoMIPS (lpj=5984256)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
ftrace: allocating 17687 entries in 52 pages
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x804ab220 - 0x804ab278
CPU1: failed to come online
Brought up 1 CPUs
SMP: Total of 1 processors activated (1196.85 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
NET: Registered protocol family 16
fpga bridge driver
DMA: preallocated 256 KiB pool for atomic coherent allocations
L310 cache controller enabled
l2x0: 8 ways, CACHE_ID 0x410030c9, AUX_CTRL 0x32460000, Cache size: 524288 B
syscon fffef000.l2-cache: regmap [mem 0xfffef000-0xfffeffff] registered
syscon ffd05000.rstmgr: regmap [mem 0xffd05000-0xffd05fff] registered
syscon ffc25000.sdrctl: regmap [mem 0xffc25000-0xffc25fff] registered
syscon ff800000.l3regs: regmap [mem 0xff800000-0xff800fff] registered
syscon ffd08000.sysmgr: regmap [mem 0xffd08000-0xffd0bfff] registered
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
altera_hps2fpga_bridge fpgabridge.2: fpga bridge [hps2fpga] registered as device hps2fpga
altera_hps2fpga_bridge fpgabridge.2: init-val not specified
altera_hps2fpga_bridge fpgabridge.3: fpga bridge [lshps2fpga] registered as device lwhps2fpga
altera_hps2fpga_bridge fpgabridge.3: init-val not specified
altera_hps2fpga_bridge fpgabridge.4: fpga bridge [fpga2hps] registered as device fpga2hps
altera_hps2fpga_bridge fpgabridge.4: init-val not specified
bio: create slab <bio-0> at 0
FPGA Mangager framework driver
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
Switching to clocksource timer0
NET: Registered protocol family 2
TCP established hash table entries: 8192 (order: 4, 65536 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
TCP: reno registered
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
arm-pmu arm-pmu: PMU:CTI successfully enabled for 1 cores
NFS: Registering the id_resolver key type
Key type id_resolver registered
Key type id_legacy registered
NTFS driver 2.1.30 [Flags: R/W].
jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
msgmni has been set to 1984
io scheduler noop registered (default)
Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
ffc02000.serial0: ttyS0 at MMIO 0xffc02000 (irq = 194) is a 16550A
console [ttyS0] enabled
altera_fpga_manager ff706000.fpgamgr: fpga manager [Altera FPGA Manager] registered as minor 0
brd: module loaded
denali-nand-dt ff900000.nand: Dump timing register values:acc_clks: 4, re_2_we: 20, re_2_re: 20
we_2_re: 12, addr_2_data: 14, rdwr_en_lo_cnt: 2
rdwr_en_hi_cnt: 2, cs_setup_cnt: 2
ONFI param page 0 valid
ONFI flash detected
NAND device: Manufacturer ID: 0x2c, Chip ID: 0xda (Micron MT29F2G08ABAEAWP), 256MiB, page size: 2048, OOB size: 64
Bad block table found at page 131008, version 0x01
Bad block table found at page 130944, version 0x01
5 ofpart partitions found on MTD device denali-nand
Creating 5 MTD partitions on "denali-nand":
0x000000000000-0x000001000000 : "NAND Flash Boot Area 16MB"
0x000001000000-0x000002000000 : "NAND Flash Boot Area backup1 16MB"
0x000002000000-0x000003000000 : "NAND Flash Boot Area backup2 16MB"
0x000003000000-0x00000b000000 : "NAND Flash jffs2 Root Filesystem 128MB"
0x00000b000000-0x000010000000 : "NAND Flash jffs2 Root Filesystem 80MB"
dw_spi_mmio fff00000.spi: master is unqueued, this is deprecated
CAN device driver interface
c_can_platform ffc00000.d_can: invalid resource
c_can_platform ffc00000.d_can: control memory is not used for raminit
c_can_platform ffc00000.d_can: c_can_platform device registered (regs=bf8dc000, irq=163)
stmmac_hw_init: 1000M
stmmac - user ID: 0x10, Synopsys ID: 0x37
Ring mode enabled
DMA HW capability register supported
Enhanced/Alternate descriptors
Enabled extended descriptors
RX Checksum Offload Engine supported (type 2)
TX Checksum insertion supported
Enable RX Mitigation via HW Watchdog Timer
libphy: stmmac: probed
eth0: PHY ID 0007c0f1 at 0 IRQ POLL (stmmac-0:00) active
usbcore: registered new interface driver usb-storage
mousedev: PS/2 mouse device common for all mice
i2c /dev entries driver
Synopsys Designware Multimedia Card Interface Driver
dwmmc_socfpga ff704000.dwmmc0: couldn't determine pwr-en, assuming pwr-en = 0
dwmmc_socfpga ff704000.dwmmc0: Using internal DMA controller.
dwmmc_socfpga ff704000.dwmmc0: Version ID is 240a
dwmmc_socfpga ff704000.dwmmc0: DW MMC controller at irq 171, 32 bit host data width, 1024 deep fifo
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
dwmmc_socfpga ff704000.dwmmc0: 1 slots initialized
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
oprofile: using arm/armv7-ca9
TCP: cubic registered
NET: Registered protocol family 10
sit: IPv6 over IPv4 tunneling driver
NET: Registered protocol family 17
NET: Registered protocol family 15
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20120528 t)
can: netlink gateway (rev 20130117) max_hops=1
8021q: 802.1Q VLAN Support v1.8
Key type dns_resolver registered
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
ThumbEE CPU extension supported.
Registering SWP/SWPB emulation handler
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
jffs2: Empty flash at 0x01397ea4 ends at 0x01398000
VFS: Mounted root (jffs2 filesystem) on device 31:3.
devtmpfs: mounted
Freeing unused kernel memory: 328K (8065b000 - 806ad000)
eth0: device MAC address 56:d9:6b:09:dc:23
init phy ok
PHY DMA init OK
eth0: device MAC address 00:1d:6c:ed:31:bf
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
libphy: stmmac-0:00 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
In axi fpga driver!
Original value in RESET_MANAGER_BASE_ADDR + BRGMODRST_ADDR is 0x0
request_mem_region OK!
AXI fpga dev virtual address is 0xbf942000
*base_vir_addr = 0xc504
In fpga mem driver!
request_mem_region OK!
fpga mem virtual address is 0xc0000000
eth0: device MAC address 00:1d:6c:ed:31:bf
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
eth0: device MAC address 00:1d:6c:ed:31:bf
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
libphy: stmmac-0:00 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
prepare send works thread on chain[0]
prepare send works thread on chain[1]
prepare send works thread on chain[2]
prepare send works thread on chain[3]
prepare send works thread on chain[4]
prepare send works thread on chain[5]
prepare send works thread on chain[6]
prepare send works thread on chain[7]
prepare send works thread on chain[8]
prepare send works thread on chain[9]
prepare send works thread on chain[10]
prepare send works thread on chain[11]
prepare send works thread on chain[12]
prepare send works thread on chain[13]
prepare send works thread on chain[14]
prepare send works thread on chain[15]
Find hashboard on Chain[0]
Find hashboard on Chain[2]
Find hashboard on Chain[3]
chain[0] has no freq in PIC! Will use default freq=600 and jump over...
chain[2] has no freq in PIC! Will use default freq=600 and jump over...
chain[3] has no freq in PIC! Will use default freq=600 and jump over...
set command mode to VIL
singleBoardTest: AsicType = 1387
singleBoardTest: asicNum = 64
singleBoardTest: real AsicNum = 63
--- check asic number
set_baud=1
The min freq=700
set real timeout 52, need sleep=379392
disable_pic_dac on chain[0] testDone[0]=1
disable_pic_dac on chain[2] testDone[2]=1
disable_pic_dac on chain[3] testDone[3]=1
search freq for 1 times, completed chain = 3, total chain num = 3
restart Miner chance num=2
waiting for send_func to exit of chain[0]
waiting for send_func to exit of chain[1]
waiting for send_func to exit of chain[2]
waiting for send_func to exit of chain[3]
waiting for send_func to exit of chain[4]
waiting for send_func to exit of chain[5]
waiting for send_func to exit of chain[6]
waiting for send_func to exit of chain[7]
waiting for send_func to exit of chain[8]
waiting for send_func to exit of chain[9]
waiting for send_func to exit of chain[10]
waiting for send_func to exit of chain[11]
waiting for send_func to exit of chain[12]
waiting for send_func to exit of chain[13]
waiting for send_func to exit of chain[14]
waiting for send_func to exit of chain[15]
waiting for receive_func to exit!
waiting for pic heart to exit!
Start bmminer ...
Chain[J1] has no freq in PIC, set default freq=600M
Chain[J1] has no core num in PIC
Chain[J3] has no freq in PIC, set default freq=600M
Chain[J3] has no core num in PIC
Chain[J4] has no freq in PIC, set default freq=600M
Chain[J4] has no core num in PIC
read PIC voltage=897 on chain[0]
Chain:0 chipnum=63
Chain[J1] voltage added=0.0V
Chain[J1] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:0 temp offset=0
Chain:0 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:0 max freq=600
Chain:0 min freq=600
read PIC voltage=897 on chain[2]
Chain:2 chipnum=63
Chain[J3] voltage added=0.0V
Chain[J3] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:2 temp offset=0
Chain:2 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:2 max freq=600
Chain:2 min freq=600
read PIC voltage=897 on chain[3]
Chain:3 chipnum=62
Chain[J4] voltage added=0.0V
Chain[J4] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:3 temp offset=0
Chain:3 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600
Chain:3 max freq=600
Chain:3 min freq=600
Miner fix freq ...
read PIC voltage=897 on chain[0]
Chain:0 chipnum=63
Chain[J1] voltage added=0.0V
Chain[J1] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:0 temp offset=0
Chain:0 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:0 max freq=600
Chain:0 min freq=600
read PIC voltage=897 on chain[2]
Chain:2 chipnum=63
Chain[J3] voltage added=0.0V
Chain[J3] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:2 temp offset=0
Chain:2 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:2 max freq=600
Chain:2 min freq=600
read PIC voltage=897 on chain[3]
Chain:3 chipnum=62
Chain[J4] voltage added=0.0V
Chain[J4] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:3 temp offset=0
Chain:3 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600
Chain:3 max freq=600
Chain:3 min freq=600
max freq = 600
prepare send works thread on chain[0]
prepare send works thread on chain[1]
prepare send works thread on chain[2]
prepare send works thread on chain[3]
prepare send works thread on chain[4]
prepare send works thread on chain[5]
prepare send works thread on chain[6]
prepare send works thread on chain[7]
prepare send works thread on chain[8]
prepare send works thread on chain[9]
prepare send works thread on chain[10]
prepare send works thread on chain[11]
prepare send works thread on chain[12]
prepare send works thread on chain[13]
prepare send works thread on chain[14]
prepare send works thread on chain[15]
do 12 8xPatten test for 1 times
Find hashboard on Chain[0]
Find hashboard on Chain[2]
Find hashboard on Chain[3]
use PIC voltage=897 on chain[0]
now set pic voltage=79 on chain[0]
use PIC voltage=897 on chain[2]
now set pic voltage=79 on chain[2]
use PIC voltage=897 on chain[3]
now set pic voltage=79 on chain[3]
enable_pic_dac on chain[0]
enable_pic_dac on chain[2]
enable_pic_dac on chain[3]
set command mode to VIL
doHeatBoard: AsicType = 1387
doHeatBoard: asicNum = 64
doHeatBoard: real AsicNum = 63
--- check asic number
check chain[0]: asicNum = 63
check chain[2]: asicNum = 63
check chain[3]: asicNum = 62
Error: The AsicNum=62 on chain[3]!
Set Freq of PIC for Test Patten on Chain[0]
Set Freq of PIC for Test Patten on Chain[2]
Set Freq of PIC for Test Patten on Chain[3]
set_baud=1
anyone got a older firmware file for s9 b9 ? I didn't read the entire log, but we had a similar situation at our mine. I don't know if this will work for you, but it worked for us. Go into your upgrade settings and click the reset button. After we reset and rebooted, this problem went away. |
SEGMINING Miner Co-Location in Vancouver, WA $75/KW/Month with VPN access to your hardware http://segmining.com |
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Ninetoe
Newbie
Offline
Activity: 45
Merit: 0
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October 19, 2016, 10:25:19 PM |
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a little update.
after 18 hours it started hashing with no intervention from me, but was showing all temps as 0 and fans going crazy, but hashrate seems ok.
hope bitmain can get back to me with a earlier firmware
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sidehack
Legendary
Offline
Activity: 3402
Merit: 1865
Curmudgeonly hardware guy
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October 19, 2016, 10:57:16 PM |
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I haven't really probed but based on behavior I would guess the micro toggles the main buck's enable line. This was not on the S7. I would also guess but I haven't confirmed that the buck might be hardwired for a particular voltage. The one I looked at today, two adjacent boards had two different voltages. Since it's someone else's machines I'm not willing to poke around on 'em to see what goes where and does what, but if the buck is the same as S7 (looks like it at a glance) the DPOT is left unpopulated. I'd be interested to know if that's the case on the new version. If any of y'all have a board shoot craps and open it up it'd be great to get some high-res pictures of the regulator portion of the board.
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NotFuzzyWarm (OP)
Legendary
Online
Activity: 3822
Merit: 2706
Evil beware: We have waffles!
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October 20, 2016, 01:14:41 AM
Last edit: October 20, 2016, 01:36:46 AM by NotFuzzyWarm |
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I haven't really probed but based on behavior I would guess the micro toggles the main buck's enable line. This was not on the S7. I would also guess but I haven't confirmed that the buck might be hardwired for a particular voltage. The one I looked at today, two adjacent boards had two different voltages. Since it's someone else's machines I'm not willing to poke around on 'em to see what goes where and does what, but if the buck is the same as S7 (looks like it at a glance) the DPOT is left unpopulated. I'd be interested to know if that's the case on the new version. If any of y'all have a board shoot craps and open it up it'd be great to get some high-res pictures of the regulator portion of the board.
Tell ya what, considering that if a board in my b17 miner goes wonky I'll see what Bitmain Warranty can do about it vs sending to China, I'll look tomorrrow. Reason is this post in the Official s9 thread https://bitcointalk.org/index.php?topic=1493601.msg16620404#msg16620404Leads me to wonder if the PIC/MCU/whatever now has a direct link to the Vcore regulator... From what I can tell on older s9's the regulator is identical to an s7. Even have a nice set of pins that can probably be used to program the voltage like an s7. edit: Have you had a chance to look at disassembled s9 (batch 17?) code at https://onlinedisassembler.com/odaweb/HP7GAkIN ? Way out of my league to dig into but the index points to many many interesting bits I don't recall seeing before... Damn that brings back memories! I haven't dealt with assembly code since the mid-1970-s through maybe 1982. Motorola 6800, Z80 and a few others. Trying to cram functional work-with-the-world code into maybe 128k leaving 32k of changeable user memory if you were lucky... Good way to make someone feel real old there... |
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NotFuzzyWarm (OP)
Legendary
Online
Activity: 3822
Merit: 2706
Evil beware: We have waffles!
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October 20, 2016, 01:24:44 AM |
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Anyone here know how to ssh into the s9 and grab a copy of the on-board (part of the ARM based SOC) flash firmware aka the Factory Reset image that the controller uses when mounting the working partition(s)? Sadly, working knowledge of any 'UX is not one of the many hats I wear  For 1 it would make for a damn fine way to have a real backup vs just a settings file the 'backup' function does for us. For 1 I suppose the resulting file should be a directly usable xxxx.tar.gz file. |
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NotFuzzyWarm (OP)
Legendary
Online
Activity: 3822
Merit: 2706
Evil beware: We have waffles!
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October 20, 2016, 09:04:42 PM
Last edit: October 22, 2016, 04:42:12 PM by NotFuzzyWarm |
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I haven't really probed but based on behavior I would guess the micro toggles the main buck's enable line. This was not on the S7. I would also guess but I haven't confirmed that the buck might be hardwired for a particular voltage. The one I looked at today, two adjacent boards had two different voltages. Since it's someone else's machines I'm not willing to poke around on 'em to see what goes where and does what, but if the buck is the same as S7 (looks like it at a glance) the DPOT is left unpopulated. I'd be interested to know if that's the case on the new version. If any of y'all have a board shoot craps and open it up it'd be great to get some high-res pictures of the regulator portion of the board.
Pics of s9 b17 Vcore regulator section: Font side At least this looks near pristine!. That same area on many/most of my older s9's sorta look um, like someone spit on it and it dried... (seriously, doubt that is it more likely flux residue from bad cleaning). Nasty looking and highly unprofessional.  Back side showing no U2 DPOT. Also R17 coming from a bus of some sort going to U2's pin-6 along with R101 and R102 are missing as well. 101-102 run between the DPOT and programming plug P1 pins 1 & 2 that was used for Sidehacks s7 undervolting mod. To me, bottom line is that the PIC has direct coms with the Vcore regulator which from a design point makes perfect sense. I mean, since many/most regulators have internal EPROM or flash to store safe startup values and are quite happy to talk to a micro-controller once the uC wakes up, why add another layer (the DPOT) to things? Have all s9's been like this? Guess I gotta dig up pics of the bad s9 boards I sent to Bitmain Warranty...  Now to wait for the miner to finish playing with itself and get back to work.... edit: And 15min later -- back to full speed  |
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not.you
Legendary
Offline
Activity: 1726
Merit: 1018
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October 20, 2016, 11:17:33 PM |
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Anyone here know how to ssh into the s9 and grab a copy of the on-board (part of the ARM based SOC) flash firmware aka the Factory Reset image that the controller uses when mounting the working partition(s)? Sadly, working knowledge of any 'UX is not one of the many hats I wear For 1 it would make for a damn fine way to have a real backup vs just a settings file the 'backup' function does for us. For 1 I suppose the resulting file should be a directly usable xxxx.tar.gz file. If you are a windows person then winscp is an easy option to connect to the miner and transfer files. |
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