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Author Topic: Trying to create a FPGA miner with vanity address split-key generator  (Read 404 times)
TetraHect0rCannabinol
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December 05, 2016, 05:47:04 AM
 #1

Hi sorry to bring up a old thread, but I am trying to create a fpga miner this is the part of the code im stuck with :
https://bitcointalk.org/index.php?topic=1704597

if someone wants to help that be great, @ThePicachu any guidance ?

*Grabs a bottle of Whiskey* - Its official, Im crazyer than crazy, I Am Hect0r Baby Cheesy
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December 15, 2016, 06:56:03 PM
 #2

I've split this post from the original thread as it's quite old and this question warrants a new thread.

@OP, please update your thread title and your OP to reflect these changes.

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ShodanEnkidu
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January 03, 2017, 07:00:57 PM
 #3

Hi,

I'm not a high level programming language developer, so unfortunately I can't help you in your C problem.

But are you sure you want to implement a miner in C for the FPGA? Are you going to use a high level synthesis tool or something for this?
If you plan to implement code for the ARM processor or an embedded processor (built in the FPGA) that will not be faster then if you made it for a general PC processor.
If you want to make something (much) more effective, make it directly for the FPGA in a HDL language. You can also find coding examples for it on the web. I remember that I have seen one on opencores.org also.

Regards,
Shodan
TetraHect0rCannabinol
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January 08, 2017, 04:35:50 PM
 #4

I do plan at some point to use the arm controller / gpu also on some boards but im currently trying to write a miner for Parallella microserver, it uses c as its main libary for threading onto the Epiphany controller.

I picked that board because its new and has 18 cores to play with, im just stuck getting the right code to mine with thats all Sad

*Grabs a bottle of Whiskey* - Its official, Im crazyer than crazy, I Am Hect0r Baby Cheesy
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