"Condo" for your Avalon chips: Price Drastically Reduced!

[flyonwall]

Hi flyonwall,

I would like to ask for your opinion on BFL offer we got today at https://bitcointalk.org/index.php?topic=223571 .

They are willing to sell us (as GroupBuy) advanced 65 nm chips (4 GH/s per piece) on 100% escrow (John K.), on-time-or-deal-is-off policy.

Is developing and producing mining boards capable of running those chips more challenging than for Avalon's 110 nm ones? Would you be interested? (Avalon boards are surely to stay the top priority.)

Since, I'm refining the deal right now, I can use any suggestions about documentation, sample chips etc. I should require for you/other developers as part of the deal.

Thank you.

Hi Kernel32,
I have a Jalapeno order in place with BFL since February (Order #100016514). I will not invest any time and effort on their chip until they deliver my order. Also, once they deliver my Jalapeno, I will look inside and give you my opinion.

Edit:
They can't just jump to my order either, forgetting the rest of the people ahead of me. I will accept my Jalapeno if they decide to deliver it ahead of the others, but I will still not spend any time and effort on their chip if they simply jump through to my order. The reason is that, by this time, if they do really have chips in production, they should be delivering systems at a fast clip. They are not, so giving me a favor at the expense of others would tell me that the whole thing is suspect. I just can't believe that they are selling chips now so other outfits like me can deliver the systems, instead of having people wait for them. If this were true, would they be willing to fund me to build systems for their current customers? If they need help delivering the systems for their current customers, I can help; but they (BFL) would have to pay me first in order for me to do it.

[1714776084]

1714776084

[flyonwall]

It looks like we are the first to get a Control Unit working. This is an important step in building an Avalon system clone. Is there anybody else out there who are ahead of us?

Here's a console printout from Xilinx's iMPACT FPGA programmer, as it loaded Xiangfu's test program onto the Spartan-6. (I will post a video of the prototype Control Unit later.)

INFO:iMPACT - Current time: 6/8/2013 8:53:22 AM
// *** BATCH CMD : Program -p 1
PROGRESS_START - Starting Operation.
Maximum TCK operating frequency for this device chain: 25000000.
Validating chain...
Boundary-scan chain validated successfully.
'1': Programming device...
 LCK_cycle = NoWait.
LCK cycle: NoWait
done.
'1': Reading status register contents...

• CRC ERROR                                                              :         0
[1] IDCODE ERROR                                                           :         0
[2] DCM LOCK STATUS                                                        :         1
[3] GTS_CFG_B STATUS                                                       :         1
[4] GWE STATUS                                                             :         1
[5] GHIGH STATUS                                                           :         1
[6] DECRYPTION ERROR                                                       :         0
[7] DECRYPTOR ENABLE                                                       :         0
[8] HSWAPEN PIN                                                            :         1
[9] MODE PIN M[0]                                                          :         1
[10] MODE PIN M[1]                                                         :         1
[11] RESERVED                                                              :         0
[12] INIT_B PIN                                                            :         1
[13] DONE PIN                                                              :         1
[14] SUSPEND STATUS                                                        :         0
[15] FALLBACK STATUS                                                       :         0
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0011 1100 1110 1100
INFO:iMPACT:579 - '1': Completed downloading bit file to device.
INFO:iMPACT:188 - '1': Programming completed successfully.
 LCK_cycle = NoWait.
LCK cycle: NoWait
INFO:iMPACT - '1': Checking done pin....done.
'1': Programmed successfully.
PROGRESS_END - End Operation.
Elapsed time =      1 sec.

[zefir]

Cross-post in all threads of projects that are registered for Avalon sample chips from my order.

Delivery of sample chips seems to have started.

If you have chips ordered with me that you want to support this project with, do it now.

If you are the owner of this project, please provide me your shipping address.


Find the details here.

[flyonwall]

Been too busy working on the Control Unit and Condo Management System, I haven't had time to update. For now I am just posting here a video about the state of the Control Unit. So far I am able to write the bitstream onto the Flash PROM, and the Spartan-6 is loading the bitstream during startup.

http://www.youtube.com/watch?v=rlBKJWVvenQ

[flyonwall]

USB on Control Unit works! But there are other remaining problems. Getting there ...

[fasmax]

USB on Control Unit works! But there are other remaining problems. Getting there ...

Great work! Thanks for sharing the video.
Have you been able to look at the configuration signals with your logic analyzer?

[Foofighter]

USB on Control Unit works! But there are other remaining problems. Getting there ...

Great work! Thanks for sharing the video.
Have you been able to look at the configuration signals with your logic analyzer?

+1

really great work here!

I would also jump on your boat because it looks really promising but unfortunatly I have no chips left from group buys (I send a few to burnin and the other to K16 manufacturer).

Keep up your work!

regards
Foofighter

[flyonwall]

Have you been able to look at the configuration signals with your logic analyzer?

No, I still don't know what the P2 header is for. Any ideas? I am posting a question on the Avalon support thread.

[frontbit]

frontbit, 1, 3.24, 1BxPLhWDcaEu7JGa9vHykYs15VEEqjWhyh
(includes 10 chips from Carlos’ April 30 order from Zefir)

[fasmax]

Have you been able to look at the configuration signals with your logic analyzer?

No, I still don't know what the P2 header is for. Any ideas? I am posting a question on the Avalon support thread.

I just went through the schematic and could not find any thing connected.
Maybe its for debugging the internals of the FPGA it looks like a differential clock ,reset and something else.

[flyonwall]

I just went through the schematic and could not find any thing connected.
Maybe its for debugging the internals of the FPGA it looks like a differential clock ,reset and something else.

No, P2 is not being used at all. Avalon has just updated their pictures: https://bitcointalk.org/index.php?topic=156323.msg2488633#msg2488633
Now it's showing Version 1.5 of the card.

I have great news! The Control Unit works now. If I load the bitstream directly to the Spartan chip using JTAG, it works; however, when it's loaded from the Flash chip, it doesn't run. One of my collaborators has suggested that may be it's because, as indicated in the reference documents, some parts of the bitstream are licensed cores and cannot be made part of the bitstream. So the file that gets copied to the Flash chip is missing those licensed cores, but programming the Spartan chip directly allows the iMPACT programmer to load the licensed cores from its library. If this is the case, no problem. We will buy the license to those cores. This kind of thing is already included in my calculations for the price of each condo unit.

[flyonwall]

I will be silent (no news) for about a week. I am moving to Washington state, and am waiting for the next prototype run.

[flyonwall]

We've got a working system with a single, fully-populated hash unit (1 condo unit)!

Big, big thanks to SebastianJu for sending me a total of 11 chips.
Huge thanks to my collaborators in Ohio. They will be making an announcement soon.

I will take a video of my setup later, and show it on this thread.

[Foofighter]

Thanks for your great work! looking forward to see the video

[webwolf86]

Congratulations!

[flyonwall]

Thank you.

Here's the video from Krater Mining in Ohio, my collaborators. They are still setting up their website, and will be selling hardware WITHOUT prepay. Their target client is not necessarily those who bought chips. When you place an order and they accept it, they will deliver right away. We work together so if you order and let them know you want hosting, we can host your unit in the condo place I am preparing in Washington state.

http://vimeo.com/69838329

Edit: Note that in this demo the Krater Mining team has two hash units running!

Edit: More precise wording than "without prepay" is that Krater Mining will be accepting orders as soon as their website is up, and the systems will be built as soon as they get their 10,000 chip order from Bitsyncom (Avalon). For any questions, please PM Mike4747. They will also be opening a thread in this forum soon.

[Foofighter]

n1 video, thank you very much!

[flyonwall]

We actually have two working prototype systems, one in Ohio and another here in Washington. This video has poor quality, but in it I try to show both the CONFIG_P and REPORT_P signals from the chips. This system in Washington has only one hash unit connected to the control unit.

http://youtu.be/L0Hfh9OTmV4


Edit: The are four probes, but on the screen it's showing only the CONFIG_P and REPORT_P signals.

More edit: The information provided here should help those who are designing their own boards.

[fasmax]

We actually have two working prototype systems, one in Ohio and another here in Washington. This video has poor quality, but in it I try to show both the CONFIG_P and REPORT_P signals from the chips. This system in Washington has only one hash unit connected to the control unit.

http://youtu.be/L0Hfh9OTmV4


Edit: The are four probes, but on the screen it's showing only the CONFIG_P and REPORT_P signals.

More edit: The information provided here should help those who are designing their own boards.

Thanks for sharing this video.

In your example capture you got a result after about .65 seconds but I don't think that the Avalon chips had finished testing the entire nonce range.
Just because you got a report doesn't mean that the ASIC is done it would be possible to get more reports so it finishes going through the nonce range.
It the miner goes through all the nonce range and doesn't get a report new work is loaded into the ASIC chips.
For 10 chips timing seems about right.
At least that's how I think is works but I could be wrong.

[flyonwall]

Thanks for sharing this video.

In your example capture you got a result after about .65 seconds but I don't think that the Avalon chips had finished testing the entire nonce range.
Just because you got a report doesn't mean that the ASIC is done it would be possible to get more reports so it finishes going through the nonce range.
It the miner goes through all the nonce range and doesn't get a report new work is loaded into the ASIC chips.
For 10 chips timing seems about right.
At least that's how I think is works but I could be wrong.

You are right. The ten chips divide the work item among themselves. If the range given in the work item happens to not include the target, then none of the chips would pull the report line down, and the Spartan times out. The timeout seems to be about 1.6 secs in this particular case. If any of the chips find a good result, then it pulls the report line down, and hands the good result to the Spartan chip. All the other chips then "lose" and their work basically discarded. This means that the report line can be pulled down anytime after the work item is distributed among the Avalon chips: there is no fixed time by which the Spartan chip can expect this signal to come, but it can set a maximum wait time.