An estimate of fpga performance

[mimarob]

Hello!

I converted the sha256 available in opencores.org into vhdl, just to see what to expect.

I got an xc3s500E about 1/3 full on the logic gates, so with a shoe horn one could maybe fit 3 cores into one of these. That does not include the communications with the host, nor the "less than" compare if the result is below the current threshhold.

 (I used an antique ISE (8.something) so maybe newer versions will compute better).

Assuming a maximum of 300 MHz and about 80 cycles to read in, process and output the result (8 + 64 +

You'd get 3*300/80 ~= 11 Mhash/s

This device can be had on a nice DIP socket (GOP modules) at about 60 EUR.

If you want to run this simulation (only tried on Linus), you need ghdl and gtkwave packages (and probably some more stuff that I forgot).

The tar in the attachement contains the synthable file sha256.vhd and the test_sha256.vhd and a simple Makefile.

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[grondilu]

Ok but in order to mine don't you need a full VHDL implementation of the miner code ?
Because if you must communicate between your PC and your FPGA, this might slow it down quite a lot.

Also I don't understand :  have you just done simulations or have you tried on the actual device ?

[bytemaster]

How does this compare to a GPU?   

[jgarzik]

Because if you must communicate between your PC and your FPGA, this might slow it down quite a lot.

As long as the FPGA performs millions of hashes for each "call" (host sents work to FPGA), host<->FPGA communication cost is small.

[bitcoin2]

Nice 
A full implementation would be great!

[bitcoin2]

How does this compare to a GPU?   

One AMD radeon 5970 (570 Mhash/s) = ~ 50 * xc3s500E (11 Mhash/s). But with FPGAs the Mhash/W should be better as with GPUs.

[jgarzik]

One AMD radeon 5970 (570 Mhash/s) = ~ 50 * xc3s500E (11 Mhash/s). But with FPGAs the Mhash/W should be better as with GPUs.

I'm not sure what Mhash/W is.  But, GPUs are ASIC so they begin with a significant advantage over FPGAs.

[bitcoin2]

One AMD radeon 5970 (570 Mhash/s) = ~ 50 * xc3s500E (11 Mhash/s). But with FPGAs the Mhash/W should be better as with GPUs.

I'm not sure what Mhash/W is.  But, GPUs are ASIC so they begin with a significant advantage over FPGAs.

Mhash/watt. FPGAs should be has a better power efficients than GPUs. ASIC (Application-specific integrated circuit) for mining only (like Deep Crack for DES) would be the greatest variant, but this is very expensive in development (maybe 300,000 USD?).

[GeorgeH]

Under my rough calculations, the highest end Virtex 5 could hit 40-50 mhps. At $3000+ for a PCIE dev board, it is far more cost effective to buy ATI video cards.

Edit:

Of course, if one were to connect a bunch of these things in parallel, they could make a big dent, ie:
http://www.sciengines.com/copacobana/

[mimarob]

hello again!

Just to clarify, I did run the program under simulation only, but I also compiled the module into the Xilinx synthesis tool (ISE) just to see how much space it would take in the chip. (I don't even own a spartan fpga :-)

A full implementation.. well I'm just trying to understand the criteria for a found block, not being an expert in cryptography. This will also need to be in hardware, I think, so the fpga only reports back when it has found something.

I just checked in at the calculator (http://www.alloscomp.com/bitcoin/calculator.php).
What is the correlation between the "difficulty factor" and the "hash target"? Why do we use two concepts?

I also checked in to the bitcoin code, but it seems that the routine I'm trying to accelerate (ScanHash_CryptoPP) is only checking for a certain number of zeroes and then returning.

Where is the code that checks if you've found a block? I guess it would only be a simple less-than compare in the hardware.

The code would also need to contain some uart comms or similar, I thought of broadcasting the request to all devices and then daisy-chaining the results back so that the "winning" device could break the chain and report back to the host computer.

[jib]

Difficulty = (2^224)/target. They're just two representations of the same thing. To check if you've found a block, you check if the hash is less than the target.

[jgarzik]

I also checked in to the bitcoin code, but it seems that the routine I'm trying to accelerate (ScanHash_CryptoPP) is only checking for a certain number of zeroes and then returning.

Correct.  The scanner performs a fast-path check, and then a more exhaustive check if the fast-path check exits the scanner loop.

Where is the code that checks if you've found a block? I guess it would only be a simple less-than compare in the hardware.

See CheckWork().  It is a less-than compare, on an unsigned 256-bit little endian integer.

[romkyns]

http://www.dinigroup.com/product/data/DNDPB_S327/images/board_front6.jpg

Drool...

By my own estimates, this thing could generate a block every few hours at the current difficulty. I doubt it would cost less than $25k-$50k though...

(source: http://www.dinigroup.com/new/products.html)

[mimarob]

Yeah that seems about right, that altera board contains 12 times as many 4 input lut's as an xc3s500 spartan module in the GOP module. 12 x 27 = 324 times the 11 MHash in my calcs => 3564000 khash/sec input in the calculator gives you 4 hours for a block. Counting at 2000 blocks per year you get 100000 BTC or $25k a year assuming moderate difficulty increase.

So I guess the graphics cards beat the crap out of the fpga's. But what about power consumption? Also the graphics cards need a motherboard, host cpu etc.

Wonder how far you could optimize the gate count?

Putting a few hundreds of these DIP formfactor boards together would also give you a priceless 80's feeling :-)

http://shop.trenz-electronic.de/catalog/product_info.php?products_id=81

[bitcoin2]

ArtForz has developed sha256 ASICs and let them (100 pieces) manufacturing for about $500/engine. This ASICs beats 5970 on hash/W by a factor of 6 but loses to 5970 on hash/$ by about a factor of 3, he said. These ASICs are not exactly a real standard cell ASIC but "metal-layer defined ASIC, basically FPGA without the FP part" (source: #bitcoin-dev).

[MoonShadow]

ArtForz has developed sha256 ASICs and let them (100 pieces) manufacturing for about $500/engine. This ASICs beats 5970 on hash/W by a factor of 6 but loses to 5970 on hash/$ by about a factor of 3, he said. These ASICs are not exactly a real standard cell ASIC but "metal-layer defined ASIC, basically FPGA without the FP part" (source: #bitcoin-dev).

What kind of ASIC is it?  Is this a custom PCI card?  Would higher production volumes improve the price point?  I'm interested in this, as a purpose made PCI card would be as big a boon as buying an expensive GPU.

[bitcoin2]

ArtForz has developed sha256 ASICs and let them (100 pieces) manufacturing for about $500/engine. This ASICs beats 5970 on hash/W by a factor of 6 but loses to 5970 on hash/$ by about a factor of 3, he said. These ASICs are not exactly a real standard cell ASIC but "metal-layer defined ASIC, basically FPGA without the FP part" (source: #bitcoin-dev).

What kind of ASIC is it?  Is this a custom PCI card?  Would higher production volumes improve the price point?  I'm interested in this, as a purpose made PCI card would be as big a boon as buying an expensive GPU.

ArtForz expect the arrive in february:
https://stuff.caurea.org/irssi/freenode/%23bitcoin-dev/2010/12/%23bitcoin-dev-2010-12-20.log : 18:36

Maybe the first step to develop a ASIC is this vhdl code. I don't believe that ArtForz will give us his code. If we put money together, maybe we could have enough money to let manufacturing a real ASIC.

[Cdecker]

Just for reference again the logs for that moment: http://veritas.maximilianeum.ch/bitcoin/irc/logs/2010/12/20#l2461

[GeorgeH]

Just for reference again the logs for that moment: http://veritas.maximilianeum.ch/bitcoin/irc/logs/2010/12/20#l2461

Thanks, that was a good read.

[grondilu]

If some people created a bitcoin-dedicated ASIC, I'd be amazed.  It would be a strong indicator about how involved are some people into the bitcoin project.