[VMC] Official Virtual Mining Corporation - EXPOSED

[GalaxyASIC]

1) eASIC will not make 16GH/s bitcoin mining chip for VMC because amount of logic in eASIC products is only enough for 400-1,600 MH, 10-40x less than VMC advertizing.
2) eASIC products are based on technology that uses many times more than 1W per GH when doing bitcoin mining

It will be more like 1.6GH/s, 10 times less performance at same higher power and cost.

VMC's Fast-Hash-One with the "Worlds Fastest Bitcoin Mining Chip" @ 16 GH/s and < 12 Watts of power.

Now 256 GH/s For $3,999 Prepaid Pre-Order < 400 Watts of power shipping in October/November 2013

Limited Number of TH/s in the October/November delivery date, so order now.

http://www.virtualminingcorp.com

Shopping Cart Direct Link:

http://virtualminingcorp.com/shop1/index.php?id_product=10&controller=product

Edit: @ Bargraphics
http://www.easic.com/high-speed-transceivers-low-cost-power-fpga-nre-asic-45nm-easic-nextreme-2/easic-nextreme-2-devices-packages/

Maximum eCells 737,280 which is more or less comparable to 700,000 cells on FPGA, Spartan-6 45nm 150,000 cells was doing ~ 200MH
700,000 / 150,000 * 200MH = 930MH even if 70% higher clock on eASIC would be possible it still be only 1.6GH/s

[1714162588]

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[1714162588]

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[1714162588]

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[1714162588]

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[CryptoCluster]

You again?

Last time you were arguing that Bitfury cannot achieve such low W/GH ratio... Maybe stop flaming your competition and show something yourself?

Your marketing skills resembles BFL Josh.

[GalaxyASIC]

You again?

Last time you were arguing that Bitfury cannot achieve such low W/GH ratio... Maybe stop flaming your competition and show something yourself?

Your marketing skills resembles BFL Josh.

And he didn't achieved all the parameters that were initially advertized, 5GH at 0.6V and < 1W/GH, only two parameter 0.6V at 1/5 performance and one that was on a betting site that it will do <1W/GH, but it only run at less than half performance.

Don't get me wrong BitFury's chip still seems very impressive. But VMC's stuff is just nonsense.

[Exocyst]

Your complaints seem to me to be based off eASIC's 45nm offering, but ActiveMining (VMC) is reportedly contracting them to design a 28nm chip. Perhaps their 28nm process is still behind-the-scenes as it isn't described on eASIC's website from what I could find, so I doubt you have any idea that their 28nm process is capable of.

The OP is not based on sound understanding of what ActiveMining (VMC) has contracted eASIC to produce.

Wrap it up, nothing to see here.

[GalaxyASIC]

I don't care about VMC share, never bought or buy anything of theirs, they obviously incompetent.

Call eASIC and ask them yourself: 1) How your 45nm product compare to Xilinx Virtex-6 40nm FPGA with 750,000 logic cells?
2) How your upcoming 28nm products compare in logic capacity to Virtex -7 28nm FPGA.

On both they will answer that it will be about the same, but they can run it slightly faster. So what VMC will get is FPGA replacement.

VMC said that by end of 2013 it will be 45nm chip, since eASIC 28nm product will not be even out, and then they will pay another NRE in 2014 to get 28nm chip.

[BBQKorv]

What, a known ASIC-scammer is accusing other people of some wrong doing. Get your own side fixed first sir.

[DeathAndTaxes]

Your complaints seem to me to be based off eASIC's 45nm offering, but ActiveMining (VMC) is reportedly contracting them to design a 28nm chip. Perhaps their 28nm process is still behind-the-scenes as it isn't described on eASIC's website from what I could find, so I doubt you have any idea that their 28nm process is capable of.

Well not saying it is or isn't a possible but a die shrink at most means 2x the transistors for the same die space and in theory double the efficiency (MH/W and MH/$).  As a pratical matter nobody gets full theretical boost.  A 50%-70% improvement would be more realistic.

[VolanicEruptor]

Your complaints seem to me to be based off eASIC's 45nm offering, but ActiveMining (VMC) is reportedly contracting them to design a 28nm chip. Perhaps their 28nm process is still behind-the-scenes as it isn't described on eASIC's website from what I could find, so I doubt you have any idea that their 28nm process is capable of.

The OP is not based on sound understanding of what ActiveMining (VMC) has contracted eASIC to produce.

Wrap it up, nothing to see here.

http://www.easic.com/easic-contact/28-nm-registration/

[VolanicEruptor]

Sit on the main slideshow style page of easic.com for a minute, and you will see 28nm clearly advertised

[vlaoou321]

Your complaints seem to me to be based off eASIC's 45nm offering, but ActiveMining (VMC) is reportedly contracting them to design a 28nm chip. Perhaps their 28nm process is still behind-the-scenes as it isn't described on eASIC's website from what I could find, so I doubt you have any idea that their 28nm process is capable of.

The OP is not based on sound understanding of what ActiveMining (VMC) has contracted eASIC to produce.

Wrap it up, nothing to see here.

http://www.easic.com/easic-contact/28-nm-registration/

How to prove ATMC and EASIC cooperation?

[redbeans2012]

Your complaints seem to me to be based off eASIC's 45nm offering, but ActiveMining (VMC) is reportedly contracting them to design a 28nm chip. Perhaps their 28nm process is still behind-the-scenes as it isn't described on eASIC's website from what I could find, so I doubt you have any idea that their 28nm process is capable of.

The OP is not based on sound understanding of what ActiveMining (VMC) has contracted eASIC to produce.

Wrap it up, nothing to see here.

http://www.easic.com/easic-contact/28-nm-registration/

How to prove ATMC and EASIC cooperation?

He has posted some scans of the documents between the two companies

[VolanicEruptor]

Your complaints seem to me to be based off eASIC's 45nm offering, but ActiveMining (VMC) is reportedly contracting them to design a 28nm chip. Perhaps their 28nm process is still behind-the-scenes as it isn't described on eASIC's website from what I could find, so I doubt you have any idea that their 28nm process is capable of.

The OP is not based on sound understanding of what ActiveMining (VMC) has contracted eASIC to produce.

Wrap it up, nothing to see here.

http://www.easic.com/easic-contact/28-nm-registration/

How to prove ATMC and EASIC cooperation?

that's why you do your own due diligence, because nobody else can tell you..

[GalaxyASIC]

Issue is not that VMC had talked to eASIC, talking to a company is easy. But that eASIC can't and will not produce anything close to 16GH/s as a single chips and specially at a ridiculous power of <12W per chip.

If they could then I would have already had their chips in my hands last month. I had spoke with them several month back on the highest level.
For the past 5 month, I had spoke with almost every chip design and fab company in the world of being capable of doing this.

[joele]

I like this exposed topic, you made the price drop, now I can buy more cheaper.

[Vbs]

Edit: @ Bargraphics
http://www.easic.com/high-speed-transceivers-low-cost-power-fpga-nre-asic-45nm-easic-nextreme-2/easic-nextreme-2-devices-packages/

Maximum eCells 737,280 which is more or less comparable to 700,000 cells on FPGA, Spartan-6 45nm 150,000 cells was doing ~ 200MH
700,000 / 150,000 * 200MH = 930MH even if 70% higher clock on eASIC would be possible it still be only 1.6GH/s

Lets do some napkin math then! Let's say the 28nm nextreme has like 2*737,280 = 1,474,560 eCells; using one of the 80k LUTs flying around, that's 18 mining cores per chip. With the chip running at 800MHz, that's a minimum of 14.4GH/s just to start and end this conversation.

Funny how you think Mask Customized Routing would deliver the same crappy performance MHz bottlenecks as SRAM Programmed Routing...

[GalaxyASIC]

Lets do some napkin math then! Let's say the 28nm nextreme has like 2*737,280 = 1,474,560 eCells; using one of the 80k LUTs flying around, that's 18 mining cores per chip. With the chip running at 800MHz, that's a minimum of 14.4GH/s just to start and end this conversation.

Let's NOT say nonsense.

1) Their 28nm will not be available till 2014.

2) eASIC is not likely to make bigger than 750,000 even in 28nm, because there is no market for larger then that devices. And bitcoin market is not large enough. Only benefit of 28nm for eASIC is a bit cheaper and a bit less power use.

3) What ever design you use you will need to use ~2,200 cells @ ~128 clock cycles or you use more cells and less cycles, more or less proportionally, but there is no 80 lut design that produces bitcoin result every clock cycle.

4) Internal logic in 45nm chip, which is smallest that is available, is limited to 500MHz, even if 28nm will be capable of 800MHz, you will run into thermal limit faster than you will be able to raise frequency. Your limit will be 200-350MHz

1,470,000 / 2,200 / 128 * 350 = 1,827 MH = 1.8 GH for non existent double sized chip in 2014

But wait, they said that they will deliver 16GH chip in 45nm ? - then performance is even less.

[Vbs]

Let's NOT say nonsense.

...

Yes, let's not say nonsense please. I won't bother replying more, since you clearly have no idea what you're talking about. eAsic has been developing their 28nm tech since at least 2010. Sorry!

Clearly, even the FPGA manufacturers must be all whacko with their future plans!

http://www.eejournal.com/archives/articles/20130611-altera/
Before we dive into the background too much, let’s try some numbers on for size. How about FOUR MILLION logic element (equivalents) on a single monolithic die? For reference, at 28nm Xilinx’s V2000T used several chips interconnected on a silicon interposer (at great expense) to achieve 2 million logic elements. For monolithic FPGAs, we are looking at a 4x generation-to-generation density increase.

OK, what about speed? Let’s start with SerDes. At 28nm we were awed by 28Gbps SerDes transceivers. Now - we’ve doubled again to 56Gbps. On the Fmax front - for logic implemented in the FPGA LUT fabric itself - a mind-blowing 1GHz - double the frequency of the 28nm ancestors. This is particularly surprising given that the Fmax numbers have been relatively flat for the past several generations. In the compromise between power, area, and speed - speed has been put on the back burner for a while, because, apparently, people didn’t like chips that melt. Now, our melting days must be behind us, because we’re cranking up the clock again.

No market for larger and faster devices huh? Yeah, right!

[GalaxyASIC]

Gen 10 - is from Altera nor eASIC, Alter has it's own market, because they make FPGAs, eASIC makes fixed logic devices.

a mind-blowing 1GHz - of product that you can't get for a year and which will be limited by maximum power used in bitcoin to about 350MHz and costing $30,000 per chip

[Vbs]

Gen 10 - is from Alter nor eASIC, Alter has it's own market, because they make FPGAs, eASIC makes fixed logic devices.

Wait, so there is a market for bigger and faster devices after all?

[GalaxyASIC]

Gen 10 - is from Alter nor eASIC, Alter has it's own market, because they make FPGAs, eASIC makes fixed logic devices.

Wait, so there is a market for bigger and faster devices after all?

No there is not for eASIC