Are you saying you think they lied when they specifically said it was a standard cell design and not an FPGA conversion?
Where did they say that and what did they say exactly?
You have to admit, the chip being nearly 4x the size of hashfast, worse power consumption, very fast tape out and promised post tape out implementations, apparently no interest in any tests and done by a company that promotes its hardcopy services. I dont know if they lied or what they said, but if it talks like a duck...
I believe they advertised it as a FPGA copy, but the tech guy was ripping his eyes out at having to submit it. He wanted to spend more time on it.
WTF are you talking about? They never said it was an FPGA copy. They said it was a standard cell design, and NOT and FPGA copy.
If I had any doubts, this removes it:
https://www.kncminer.com/userfiles/image/ASIC_PCB.jpgThats an altera cyclone FPGA on there. THats what you would use to prototype your design (and pcb).
THe chance that a custom asic would fit, let alone work in the same board as an altera fpga is zero.
Moreover they write underneath that picture:
We will be using these boards to fully validate the entire setup. They will consume the same power, make the same noise level, produce the same heat and run the same RTL code. The only difference will be related to hashing.Definitely an altera hardcopy implementation.
Definitely someone who doesn't know what "RTL" actually stands for, let alone what it means.
