Thx for answer. Which one of the multiplier/divider should i adjust? I have not bought it, I'm only testing it from my school
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Lucky school, it looks like a nice dev board. The PLL output clock is simply the input clock speed (usually 50MHz on the Terasic boards, but you should check the documentation) multiplied by "clk0_multiply_by" and divided by "clk0_divide_by". Pretty simple really. The fpgaminer defaults are 5 and 5, giving 50MHz. So for 100MHz you'd use 10 and 5, while for 75MHz use 15 and 10. There are limits to the range (255 I think, so nothing to worry about normally).
Have fun. And ask permission from your school before setting up a mining botnet, you wouldn't want to get into trouble
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