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Author Topic: FPGA Miner: Cannot open include file "async_receiver.v" and "async_transmitter.v  (Read 2522 times)
stewdk
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July 20, 2011, 05:54:59 AM
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I'm trying to get teknohog's port of the FPGA miner (http://forum.bitcoin.org/index.php?topic=9047.0) working on my Digilent Nexys 2 board with an XC3S500E.
I'm getting the following errors:

ERROR:HDLCompiler:281 - "C:/Users/me/Desktop/Xilinx-Serial-Miner/sources/hdl/serial.v" Line 1: Cannot open include file "async_receiver.v".
ERROR:HDLCompiler:281 - "C:/Users/me/Desktop/Xilinx-Serial-Miner/sources/hdl/serial.v" Line 2: Cannot open include file "async_transmitter.v".

I tried with both the repos at https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/Verilog_Xilinx_Port and https://github.com/teknohog/Xilinx-Serial-Miner, they both give the same errors.
It seems there are a couple files missing from the repo?
I'm using ISE 13.2

P.S. I hate to start a whole new thread for this simple question... I would have posted in the relevant thread or PM'ed teknohog, but I don't have privileges to do either - what do I have to do to un-newbify my account?

EDIT: Nevermind, I figured it out...  http://www.fpga4fun.com/files/async.zip
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tysat
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July 20, 2011, 06:31:28 AM
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P.S. I hate to start a whole new thread for this simple question... I would have posted in the relevant thread or PM'ed teknohog, but I don't have privileges to do either - what do I have to do to un-newbify my account?

FYI - http://forum.bitcoin.org/index.php?topic=15958.0
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July 20, 2011, 07:38:28 AM
 #3

Sorry about the confusion. It is mentioned in the README.txt for that project, which states:

Quote
Usage
-----

1. Download the RS232 code from

http://www.fpga4fun.com/files/async.zip

and unzip it into sources/hdl to go with the other files. Change the
clock frequency definition in both files to suit your oscillator.
https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/blob/master/projects/Verilog_Xilinx_Port/README.txt

A bit annoying, but it isn't free code. Feel free to write an open-source replacement  Cheesy

stewdk
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July 20, 2011, 02:25:18 PM
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Thanks!

Feel free to write an open-source replacement  Cheesy

I actually did a rx-only uart for a school project once in VHDL. Shouldn't be too hard to add the tx part of it.
I haven't done much of anything in verilog yet, so maybe it would be a good exercise for me to port it over to verilog... (no promises have been made, emphasize on maybe).
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July 21, 2011, 02:07:41 AM
 #5

Quote
I haven't done much of anything in verilog yet, so maybe it would be a good exercise for me to port it over to verilog... (no promises have been made, emphasize on maybe).
Don't sweat it, I was just letting you know your contributions are welcome Smiley

And just so you know, there are VHDL ports of the mining core on the public repo. So if you are curious to study how the mining core works, you can choose either variant to learn up; they follow the same ideas.

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July 23, 2011, 12:08:04 AM
 #6

Sort of related, I have successfully gotten the LX150_Test project running on a Digilent Atlys board, which has a XC6SLX45, using LOOP_LOG2=3 and running at 50MHz, and I'm presently trying to re-fit at 75MHz. Since I don't have a chipscope license I'm using the UART code mentioned here but I will be trying to write a register-based approach that should be more robust. I'm pretty new to HDL though so don't expect immediate greatness.
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