I'm trying to get teknohog's port of the FPGA miner (http://forum.bitcoin.org/index.php?topic=9047.0
) working on my Digilent Nexys 2 board with an XC3S500E.
I'm getting the following errors:
ERROR:HDLCompiler:281 - "C:/Users/me/Desktop/Xilinx-Serial-Miner/sources/hdl/serial.v" Line 1: Cannot open include file "async_receiver.v".
ERROR:HDLCompiler:281 - "C:/Users/me/Desktop/Xilinx-Serial-Miner/sources/hdl/serial.v" Line 2: Cannot open include file "async_transmitter.v".
I tried with both the repos at https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/Verilog_Xilinx_Port
, they both give the same errors.
It seems there are a couple files missing from the repo?
I'm using ISE 13.2
P.S. I hate to start a whole new thread for this simple question... I would have posted in the relevant thread or PM'ed teknohog, but I don't have privileges to do either - what do I have to do to un-newbify my account?
EDIT: Nevermind, I figured it out... http://www.fpga4fun.com/files/async.zip