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Author Topic: Transmetta  (Read 762 times)
deslok
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August 11, 2011, 03:19:58 AM
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in the spirit of mining with whatever we can has anyone considered using a efficion or crusoe cpu for bitcoin mining? they were lower power chips based on a 128 bit(crusoe) or 256 bit (efficion) vliw arcitecture it should be possible to bypass or take advantage of in some way the "code moprhing" layer that was used to translate x86 instructions into native instructions

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August 11, 2011, 03:26:14 AM
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I can't imagine that it would be worthwhile, unless someone were going to do it just for the geek cred.  Feel free, tho.

"The powers of financial capitalism had another far-reaching aim, nothing less than to create a world system of financial control in private hands able to dominate the political system of each country and the economy of the world as a whole. This system was to be controlled in a feudalist fashion by the central banks of the world acting in concert, by secret agreements arrived at in frequent meetings and conferences. The apex of the systems was to be the Bank for International Settlements in Basel, Switzerland, a private bank owned and controlled by the world's central banks which were themselves private corporations. Each central bank...sought to dominate its government by its ability to control Treasury loans, to manipulate foreign exchanges, to influence the level of economic activity in the country, and to influence cooperative politicians by subsequent economic rewards in the business world."

- Carroll Quigley, CFR member, mentor to Bill Clinton, from 'Tragedy And Hope'
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August 11, 2011, 05:24:48 AM
 #3

FYI Transmeta is bankrupt, and their CPUs are no longer produced.  I do see quite a number of their CPUs on Ebay however.

The problem here is that Transmeta's actual VLIW format is proprietary, meaning nobody can write code for it natively except Transmeta (which won't happen since they don't exist anymore).  The other fundamental issues are:
1. Old architecture, last fabbed at 130nm (slow)
2. Up to 4 parallel instructions per clock.  This would make it equivalent to SSE2 in terms of throughput per clock rate.  Their VLIW design gives them no advantage here over a modern x86 CPU.

Even if you could write your own VLIW code, this thing would be certainly slower than 1MH/s, most likely much slower.
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