ASIC Design

[cryptonix]

Hi Everyone,

I just heard of BitCoin and all the ASIC that is being built for it. I have 11 years of engineering experience designing FPGA (Altera, Xilinx, Lattice). I can do VHDL/Verilog, Simlution and everything that needs to be done to get an FPGA design going. One area I lag behind is ASIC (by ASIC I don't mean hard-copy or easy-path like solutions, but full custom).

Does anyone know what I need to learn to make the first ASIC? What Softwares do I need to learn? Any good links or tutorials? I know people with capital who can back me up, so no worries there for me.



Thanks for the help,
P.S. I know it's a bit out-of-place question, but I'm sure some people here have gone down this road and got very successful

[1715415938]

1715415938

[1715415938]

1715415938

[1715415938]

1715415938

[AlexeyK]

try WASP

https://bitcointalk.org/index.php?topic=422243.0

[cryptonix]

Thanks AlexeyK, but it doesn't have the answer I look for there...

[Ytterbium]

You need software like Cadence Encounter or Mentor Graphics Pixis.  There's some open source software like Electric if you want to mess around with physical design layout, but actually taping out a physical chip using it would be rather difficult, since it doesn't come with any design rules you would use for high end process nodes.

The real stuff comes with design rules for TSMC/GlobalFoundaries/etc - but is very expensive.

[cryptonix]

You need software like Cadence Encounter or Mentor Graphics Pixis.  There's some open source software like Electric if you want to mess around with physical design layout, but actually taping out a physical chip using it would be rather difficult, since it doesn't come with any design rules you would use for high end process nodes.

The real stuff comes with design rules for TSMC/GlobalFoundaries/etc - but is very expensive.

Thanks. Any idea what the price is for the "Design Rules"?

[klondike_bar]

You need software like Cadence Encounter or Mentor Graphics Pixis.  There's some open source software like Electric if you want to mess around with physical design layout, but actually taping out a physical chip using it would be rather difficult, since it doesn't come with any design rules you would use for high end process nodes.

The real stuff comes with design rules for TSMC/GlobalFoundaries/etc - but is very expensive.

Thanks. Any idea what the price is for the "Design Rules"?

a few million dollars' investment from design to tapeout

[Bicknellski]

Thanks AlexeyK, but it doesn't have the answer I look for there...

Not yet anyhow maybe you want to come and talk about it with us?  

[cryptonix]

Thanks AlexeyK, but it doesn't have the answer I look for there...

Not yet anyhow maybe you want to come and talk about it with us?  

What can I do or what added value can I bring?