help regarding open source bitcoin miner code

[spaphy]

Hi can someone please provide an insight to how top.vhd in the following link is functioning?

https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/blob/master/projects/VHDL_Xilinx_Port/top.vhd

It appears to me that load always contain some undefined bits as it is undefined initially and rxdata fills only 8 bits (0 to 7) of load and further these 8 bits are transferred to the bits from 8 to 15 so ultimately only 0 to 15 will contain 1s or 0s and the rest will be undefined. If this happens state and data will contain undefined values and then how the code will work?