Such a "solution" is just a waste of time, as the inductance of the supply wires (core voltage, I/O voltage and GND) would be way too high and the FPGA would not operate reliably at any decent clock, if at all.
Consider a FPGA implementation of the Bitcoin mining algorithm (double SHA-256). There are 128 rounds of 256 bits each, i.e. 32768 flip-flops, all of which switch at the same time. All these flip-flops switching at the same time causes a momentary spike in power draw. Let´s say, for the sake of argument, from about 1 Amp when no flip-flops are switching to, say, a momentary power draw of 25 Amps (est.). If there is any inductance at all in the supply wires, the momentary power draw of 25 Amps will cause the internal core voltage to sag below the minimum acceptable core voltage, and the ground level that the FPGA sees to rise.
Below minimum core voltage, correct operation of the FPGA is no longer guaranteed, as the contents of flip-flops and even the contents of the configuration registers may be lost or corrupted.
