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Author Topic: Antminer s9 not hashing noobie  (Read 122 times)
dacoin305 (OP)
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April 10, 2022, 06:57:53 AM
 #1
Hello I bought a miner in December and it worked for about 1 month after that it just stopped working. I tried to solve the issue by researching and found no solution that fixed my problem. please help or let me know what's wrong


Code:
Booting Linux on physical CPU 0x0
Initializing cgroup subsys cpuset
Linux version 3.10.31-ltsi-00003-gcf03eb9 (lzq@armdev01) (gcc version 4.7.3 20121106 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2012.11-20121123 - Linaro GCC 2012.11) ) #81 SMP Mon Apr 25 11:20:36 CST 2016
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: Altera SOCFPGA, model: Altera SOCFPGA Cyclone V
Memory policy: ECC disabled, Data cache writealloc
On node 0 totalpages: 258048
free_area_init_node: node 0, pgdat 806e5cc0, node_mem_map 8072a000
  Normal zone: 2016 pages used for memmap
  Normal zone: 0 pages reserved
  Normal zone: 258048 pages, LIFO batch:31
PERCPU: Embedded 8 pages/cpu @80f17000 s11200 r8192 d13376 u32768
pcpu-alloc: s11200 r8192 d13376 u32768 alloc=8*4096
pcpu-alloc: [0] 0 [0] 1 
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 256032
Kernel command line: mem=1008M console=ttyS0,115200 root=/dev/mtdblock3 rw rootfstype=jffs2
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 1008MB = 1008MB total
Memory: 1015844k/1015844k available, 16348k reserved, 0K highmem
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
    vmalloc : 0xbf800000 - 0xff000000   (1016 MB)
    lowmem  : 0x80000000 - 0xbf000000   (1008 MB)
    modules : 0x7f000000 - 0x80000000   (  16 MB)
      .text : 0x80008000 - 0x8065a930   (6475 kB)
      .init : 0x8065b000 - 0x806adbc0   ( 331 kB)
      .data : 0x806ae000 - 0x806e9990   ( 239 kB)
       .bss : 0x806e9990 - 0x80729384   ( 255 kB)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
Hierarchical RCU implementation.
NR_IRQS:16 nr_irqs:16 16
sched_clock: 32 bits at 100MHz, resolution 10ns, wraps every 42949ms
Console: colour dummy device 80x30
Calibrating delay loop... 1196.85 BogoMIPS (lpj=5984256)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
ftrace: allocating 17687 entries in 52 pages
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x804ab220 - 0x804ab278
CPU1: failed to come online
Brought up 1 CPUs
SMP: Total of 1 processors activated (1196.85 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
NET: Registered protocol family 16
fpga bridge driver
DMA: preallocated 256 KiB pool for atomic coherent allocations
L310 cache controller enabled
l2x0: 8 ways, CACHE_ID 0x410030c9, AUX_CTRL 0x32460000, Cache size: 524288 B
syscon fffef000.l2-cache: regmap [mem 0xfffef000-0xfffeffff] registered
syscon ffd05000.rstmgr: regmap [mem 0xffd05000-0xffd05fff] registered
syscon ffc25000.sdrctl: regmap [mem 0xffc25000-0xffc25fff] registered
syscon ff800000.l3regs: regmap [mem 0xff800000-0xff800fff] registered
syscon ffd08000.sysmgr: regmap [mem 0xffd08000-0xffd0bfff] registered
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
altera_hps2fpga_bridge fpgabridge.2: fpga bridge [hps2fpga] registered as device hps2fpga
altera_hps2fpga_bridge fpgabridge.2: init-val not specified
altera_hps2fpga_bridge fpgabridge.3: fpga bridge [lshps2fpga] registered as device lwhps2fpga
altera_hps2fpga_bridge fpgabridge.3: init-val not specified
altera_hps2fpga_bridge fpgabridge.4: fpga bridge [fpga2hps] registered as device fpga2hps
altera_hps2fpga_bridge fpgabridge.4: init-val not specified
bio: create slab <bio-0> at 0
FPGA Mangager framework driver
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
Switching to clocksource timer0
NET: Registered protocol family 2
TCP established hash table entries: 8192 (order: 4, 65536 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
TCP: reno registered
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
arm-pmu arm-pmu: PMU:CTI successfully enabled for 1 cores
NFS: Registering the id_resolver key type
Key type id_resolver registered
Key type id_legacy registered
NTFS driver 2.1.30 [Flags: R/W].
jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
msgmni has been set to 1984
io scheduler noop registered (default)
Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
ffc02000.serial0: ttyS0 at MMIO 0xffc02000 (irq = 194) is a 16550A
console [ttyS0] enabled
altera_fpga_manager ff706000.fpgamgr: fpga manager [Altera FPGA Manager] registered as minor 0
brd: module loaded
denali-nand-dt ff900000.nand: Dump timing register values:acc_clks: 4, re_2_we: 20, re_2_re: 20
we_2_re: 12, addr_2_data: 14, rdwr_en_lo_cnt: 2
rdwr_en_hi_cnt: 2, cs_setup_cnt: 2
ONFI param page 0 valid
ONFI flash detected
NAND device: Manufacturer ID: 0x2c, Chip ID: 0xda (Micron MT29F2G08ABAEAWP), 256MiB, page size: 2048, OOB size: 64
Bad block table found at page 131008, version 0x01
Bad block table found at page 130944, version 0x01
5 ofpart partitions found on MTD device denali-nand
Creating 5 MTD partitions on "denali-nand":
0x000000000000-0x000001000000 : "NAND Flash Boot Area 16MB"
0x000001000000-0x000002000000 : "NAND Flash Boot Area backup1 16MB"
0x000002000000-0x000003000000 : "NAND Flash Boot Area backup2 16MB"
0x000003000000-0x00000b000000 : "NAND Flash jffs2 Root Filesystem 128MB"
0x00000b000000-0x000010000000 : "NAND Flash jffs2 Root Filesystem 80MB"
dw_spi_mmio fff00000.spi: master is unqueued, this is deprecated
CAN device driver interface
c_can_platform ffc00000.d_can: invalid resource
c_can_platform ffc00000.d_can: control memory is not used for raminit
c_can_platform ffc00000.d_can: c_can_platform device registered (regs=bf8dc000, irq=163)
stmmac_hw_init: 1000M
stmmac - user ID: 0x10, Synopsys ID: 0x37
 Ring mode enabled
 DMA HW capability register supported
 Enhanced/Alternate descriptors
	Enabled extended descriptors
 RX Checksum Offload Engine supported (type 2)
 TX Checksum insertion supported
 Enable RX Mitigation via HW Watchdog Timer
libphy: stmmac: probed
eth0: PHY ID 0007c0f1 at 0 IRQ POLL (stmmac-0:00) active
usbcore: registered new interface driver usb-storage
mousedev: PS/2 mouse device common for all mice
i2c /dev entries driver
Synopsys Designware Multimedia Card Interface Driver
dwmmc_socfpga ff704000.dwmmc0: couldn't determine pwr-en, assuming pwr-en = 0
dwmmc_socfpga ff704000.dwmmc0: Using internal DMA controller.
dwmmc_socfpga ff704000.dwmmc0: Version ID is 240a
dwmmc_socfpga ff704000.dwmmc0: DW MMC controller at irq 171, 32 bit host data width, 1024 deep fifo
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
dwmmc_socfpga ff704000.dwmmc0: 1 slots initialized
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
oprofile: using arm/armv7-ca9
TCP: cubic registered
NET: Registered protocol family 10
sit: IPv6 over IPv4 tunneling driver
NET: Registered protocol family 17
NET: Registered protocol family 15
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20120528 t)
can: netlink gateway (rev 20130117) max_hops=1
8021q: 802.1Q VLAN Support v1.8
Key type dns_resolver registered
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
ThumbEE CPU extension supported.
Registering SWP/SWPB emulation handler
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
VFS: Mounted root (jffs2 filesystem) on device 31:3.
devtmpfs: mounted
Freeing unused kernel memory: 328K (8065b000 - 806ad000)
eth0: device MAC address 8e:ea:9e:78:44:de
init phy ok 
PHY DMA init OK
eth0: device MAC address 00:91:6b:66:c0:ed
init phy ok 
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
libphy: stmmac-0:00 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
In axi fpga driver!
Original value in RESET_MANAGER_BASE_ADDR + BRGMODRST_ADDR is 0x0
request_mem_region OK!
AXI fpga dev virtual address is 0xbf942000
*base_vir_addr = 0xc504
In fpga mem driver!
request_mem_region OK!
fpga mem virtual address is 0xc0000000
eth0: device MAC address 00:91:6b:66:c0:ed
init phy ok 
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
eth0: device MAC address 00:91:6b:66:c0:ed
init phy ok 
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
libphy: stmmac-0:00 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
prepare send works thread on chain[0]
prepare send works thread on chain[1]
prepare send works thread on chain[2]
prepare send works thread on chain[3]
prepare send works thread on chain[4]
prepare send works thread on chain[5]
prepare send works thread on chain[6]
prepare send works thread on chain[7]
prepare send works thread on chain[8]
prepare send works thread on chain[9]
prepare send works thread on chain[10]
prepare send works thread on chain[11]
prepare send works thread on chain[12]
prepare send works thread on chain[13]
prepare send works thread on chain[14]
prepare send works thread on chain[15]
Find hashboard on Chain[0]
Find hashboard on Chain[2]
Find hashboard on Chain[3]
Check chain[0] PIC fw version=0x02
Check chain[2] PIC fw version=0x02
Check chain[3] PIC fw version=0x02
chain[0] has no freq in PIC! Will use default freq=550 and jump over...
Check chain[0] PIC fw version=0x02
chain[2] has no freq in PIC! Will use default freq=550 and jump over...
Check chain[2] PIC fw version=0x02
chain[3] has no freq in PIC! Will use default freq=550 and jump over...
Check chain[3] PIC fw version=0x02
get PIC voltage=6 on chain[0], value=940
get PIC voltage=6 on chain[2], value=940
get PIC voltage=6 on chain[3], value=940
chain[0] temp offset record: 62,-79,0,0,0,0,0,0
chain[2] temp offset record: 62,-65,0,0,0,0,0,0
chain[3] temp offset record: 62,-85,0,0,0,0,0,0
check PIC voltage=940 on chain[0]
check PIC voltage=940 on chain[2]
check PIC voltage=940 on chain[3]
set command mode to VIL

singleBoardTest: AsicType = 1387

singleBoardTest: asicNum = 64

singleBoardTest: real AsicNum = 63

--- check asic number
set_baud=0, ought to be 1
The min freq=700
set real timeout 52, need sleep=379392
search freq for 1 times, completed chain = 3, total chain num = 3 
disable_pic_dac on chain[0]
disable_pic_dac on chain[2]
disable_pic_dac on chain[3]
restart Miner chance num=2
waiting for send_func to exit of chain[0]
waiting for send_func to exit of chain[1]
waiting for send_func to exit of chain[2]
waiting for send_func to exit of chain[3]
waiting for send_func to exit of chain[4]
waiting for send_func to exit of chain[5]
waiting for send_func to exit of chain[6]
waiting for send_func to exit of chain[7]
waiting for send_func to exit of chain[8]
waiting for send_func to exit of chain[9]
waiting for send_func to exit of chain[10]
waiting for send_func to exit of chain[11]
waiting for send_func to exit of chain[12]
waiting for send_func to exit of chain[13]
waiting for send_func to exit of chain[14]
waiting for send_func to exit of chain[15]
waiting for receive_func to exit!
waiting for pic heart to exit!
Start bmminer ...
This is C5 board.
Check chain[0] PIC fw version=0x02
Check chain[2] PIC fw version=0x02
Check chain[3] PIC fw version=0x02
Chain[J1] will use highest voltage=940 [6] to open core
Chain[J3] will use highest voltage=940 [6] to open core
Chain[J4] will use highest voltage=940 [6] to open core
Chain[J1] orignal chain_voltage=6 value=940
Chain[J3] orignal chain_voltage=6 value=940
Chain[J4] orignal chain_voltage=6 value=940
Chain[J1] has 63 asic
Chain[J3] has 63 asic
Chain[J4] has 63 asic
Chain[J1] has no freq in PIC, set default freq=550M
Chain[J1] has no core num in PIC
Chain[J3] has no freq in PIC, set default freq=550M
Chain[J3] has no core num in PIC
Chain[J4] has no freq in PIC, set default freq=550M
Chain[J4] has no core num in PIC
read PIC voltage=940 on chain[0]
Chain:0 chipnum=63
Chain[J1] voltage added=0.0V
Chain[J1] [minerMAC: 00:91:6b:66:c0:ed hashMAC: 00:00:00:00:00:00]
Chain:0 temp offset=0
Chain:0 base freq=100
Asic[ 0]:550 
Asic[ 1]:550 Asic[ 2]:550 Asic[ 3]:550 Asic[ 4]:550 Asic[ 5]:550 Asic[ 6]:550 Asic[ 7]:550 Asic[ 8]:550 
Asic[ 9]:550 Asic[10]:550 Asic[11]:550 Asic[12]:550 Asic[13]:550 Asic[14]:550 Asic[15]:550 Asic[16]:550 
Asic[17]:550 Asic[18]:550 Asic[19]:550 Asic[20]:550 Asic[21]:550 Asic[22]:550 Asic[23]:550 Asic[24]:550 
Asic[25]:550 Asic[26]:550 Asic[27]:550 Asic[28]:550 Asic[29]:550 Asic[30]:550 Asic[31]:550 Asic[32]:550 
Asic[33]:550 Asic[34]:550 Asic[35]:550 Asic[36]:550 Asic[37]:550 Asic[38]:550 Asic[39]:550 Asic[40]:550 
Asic[41]:550 Asic[42]:550 Asic[43]:550 Asic[44]:550 Asic[45]:550 Asic[46]:550 Asic[47]:550 Asic[48]:550 
Asic[49]:550 Asic[50]:550 Asic[51]:550 Asic[52]:550 Asic[53]:550 Asic[54]:550 Asic[55]:550 Asic[56]:550 
Asic[57]:550 Asic[58]:550 Asic[59]:550 Asic[60]:550 Asic[61]:550 Asic[62]:550 
Chain:0 max freq=550
Chain:0 min freq=550

read PIC voltage=940 on chain[2]
Chain:2 chipnum=63
Chain[J3] voltage added=0.0V
Chain[J3] [minerMAC: 00:91:6b:66:c0:ed hashMAC: 00:00:00:00:00:00]
Chain:2 temp offset=0
Chain:2 base freq=100
Asic[ 0]:550 
Asic[ 1]:550 Asic[ 2]:550 Asic[ 3]:550 Asic[ 4]:550 Asic[ 5]:550 Asic[ 6]:550 Asic[ 7]:550 Asic[ 8]:550 
Asic[ 9]:550 Asic[10]:550 Asic[11]:550 Asic[12]:550 Asic[13]:550 Asic[14]:550 Asic[15]:550 Asic[16]:550 
Asic[17]:550 Asic[18]:550 Asic[19]:550 Asic[20]:550 Asic[21]:550 Asic[22]:550 Asic[23]:550 Asic[24]:550 
Asic[25]:550 Asic[26]:550 Asic[27]:550 Asic[28]:550 Asic[29]:550 Asic[30]:550 Asic[31]:550 Asic[32]:550 
Asic[33]:550 Asic[34]:550 Asic[35]:550 Asic[36]:550 Asic[37]:550 Asic[38]:550 Asic[39]:550 Asic[40]:550 
Asic[41]:550 Asic[42]:550 Asic[43]:550 Asic[44]:550 Asic[45]:550 Asic[46]:550 Asic[47]:550 Asic[48]:550 
Asic[49]:550 Asic[50]:550 Asic[51]:550 Asic[52]:550 Asic[53]:550 Asic[54]:550 Asic[55]:550 Asic[56]:550 
Asic[57]:550 Asic[58]:550 Asic[59]:550 Asic[60]:550 Asic[61]:550 Asic[62]:550 
Chain:2 max freq=550
Chain:2 min freq=550

read PIC voltage=940 on chain[3]
Chain:3 chipnum=63
Chain[J4] voltage added=0.0V
Chain[J4] [minerMAC: 00:91:6b:66:c0:ed hashMAC: 00:00:00:00:00:00]
Chain:3 temp offset=0
Chain:3 base freq=100
Asic[ 0]:550 
Asic[ 1]:550 Asic[ 2]:550 Asic[ 3]:550 Asic[ 4]:550 Asic[ 5]:550 Asic[ 6]:550 Asic[ 7]:550 Asic[ 8]:550 
Asic[ 9]:550 Asic[10]:550 Asic[11]:550 Asic[12]:550 Asic[13]:550 Asic[14]:550 Asic[15]:550 Asic[16]:550 
Asic[17]:550 Asic[18]:550 Asic[19]:550 Asic[20]:550 Asic[21]:550 Asic[22]:550 Asic[23]:550 Asic[24]:550 
Asic[25]:550 Asic[26]:550 Asic[27]:550 Asic[28]:550 Asic[29]:550 Asic[30]:550 Asic[31]:550 Asic[32]:550 
Asic[33]:550 Asic[34]:550 Asic[35]:550 Asic[36]:550 Asic[37]:550 Asic[38]:550 Asic[39]:550 Asic[40]:550 
Asic[41]:550 Asic[42]:550 Asic[43]:550 Asic[44]:550 Asic[45]:550 Asic[46]:550 Asic[47]:550 Asic[48]:550 
Asic[49]:550 Asic[50]:550 Asic[51]:550 Asic[52]:550 Asic[53]:550 Asic[54]:550 Asic[55]:550 Asic[56]:550 
Asic[57]:550 Asic[58]:550 Asic[59]:550 Asic[60]:550 Asic[61]:550 Asic[62]:550 
Chain:3 max freq=550
Chain:3 min freq=550


Miner fix freq ...
read PIC voltage=940 on chain[0]
Chain:0 chipnum=63
Chain[J1] voltage added=0.0V
Chain[J1] [minerMAC: 00:91:6b:66:c0:ed hashMAC: 00:00:00:00:00:00]
Chain:0 temp offset=0
Chain:0 base freq=100
Asic[ 0]:550 
Asic[ 1]:550 Asic[ 2]:550 Asic[ 3]:550 Asic[ 4]:550 Asic[ 5]:550 Asic[ 6]:550 Asic[ 7]:550 Asic[ 8]:550 
Asic[ 9]:550 Asic[10]:550 Asic[11]:550 Asic[12]:550 Asic[13]:550 Asic[14]:550 Asic[15]:550 Asic[16]:550 
Asic[17]:550 Asic[18]:550 Asic[19]:550 Asic[20]:550 Asic[21]:550 Asic[22]:550 Asic[23]:550 Asic[24]:550 
Asic[25]:550 Asic[26]:550 Asic[27]:550 Asic[28]:550 Asic[29]:550 Asic[30]:550 Asic[31]:550 Asic[32]:550 
Asic[33]:550 Asic[34]:550 Asic[35]:550 Asic[36]:550 Asic[37]:550 Asic[38]:550 Asic[39]:550 Asic[40]:550 
Asic[41]:550 Asic[42]:550 Asic[43]:550 Asic[44]:550 Asic[45]:550 Asic[46]:550 Asic[47]:550 Asic[48]:550 
Asic[49]:550 Asic[50]:550 Asic[51]:550 Asic[52]:550 Asic[53]:550 Asic[54]:550 Asic[55]:550 Asic[56]:550 
Asic[57]:550 Asic[58]:550 Asic[59]:550 Asic[60]:550 Asic[61]:550 Asic[62]:550 
Chain:0 max freq=550
Chain:0 min freq=550

read PIC voltage=940 on chain[2]
Chain:2 chipnum=63
Chain[J3] voltage added=0.0V
Chain[J3] [minerMAC: 00:91:6b:66:c0:ed hashMAC: 00:00:00:00:00:00]
Chain:2 temp offset=0
Chain:2 base freq=100
Asic[ 0]:550 
Asic[ 1]:550 Asic[ 2]:550 Asic[ 3]:550 Asic[ 4]:550 Asic[ 5]:550 Asic[ 6]:550 Asic[ 7]:550 Asic[ 8]:550 
Asic[ 9]:550 Asic[10]:550 Asic[11]:550 Asic[12]:550 Asic[13]:550 Asic[14]:550 Asic[15]:550 Asic[16]:550 
Asic[17]:550 Asic[18]:550 Asic[19]:550 Asic[20]:550 Asic[21]:550 Asic[22]:550 Asic[23]:550 Asic[24]:550 
Asic[25]:550 Asic[26]:550 Asic[27]:550 Asic[28]:550 Asic[29]:550 Asic[30]:550 Asic[31]:550 Asic[32]:550 
Asic[33]:550 Asic[34]:550 Asic[35]:550 Asic[36]:550 Asic[37]:550 Asic[38]:550 Asic[39]:550 Asic[40]:550 
Asic[41]:550 Asic[42]:550 Asic[43]:550 Asic[44]:550 Asic[45]:550 Asic[46]:550 Asic[47]:550 Asic[48]:550 
Asic[49]:550 Asic[50]:550 Asic[51]:550 Asic[52]:550 Asic[53]:550 Asic[54]:550 Asic[55]:550 Asic[56]:550 
Asic[57]:550 Asic[58]:550 Asic[59]:550 Asic[60]:550 Asic[61]:550 Asic[62]:550 
Chain:2 max freq=550
Chain:2 min freq=550

read PIC voltage=940 on chain[3]
Chain:3 chipnum=63
Chain[J4] voltage added=0.0V
Chain[J4] [minerMAC: 00:91:6b:66:c0:ed hashMAC: 00:00:00:00:00:00]
Chain:3 temp offset=0
Chain:3 base freq=100
Asic[ 0]:550 
Asic[ 1]:550 Asic[ 2]:550 Asic[ 3]:550 Asic[ 4]:550 Asic[ 5]:550 Asic[ 6]:550 Asic[ 7]:550 Asic[ 8]:550 
Asic[ 9]:550 Asic[10]:550 Asic[11]:550 Asic[12]:550 Asic[13]:550 Asic[14]:550 Asic[15]:550 Asic[16]:550 
Asic[17]:550 Asic[18]:550 Asic[19]:550 Asic[20]:550 Asic[21]:550 Asic[22]:550 Asic[23]:550 Asic[24]:550 
Asic[25]:550 Asic[26]:550 Asic[27]:550 Asic[28]:550 Asic[29]:550 Asic[30]:550 Asic[31]:550 Asic[32]:550 
Asic[33]:550 Asic[34]:550 Asic[35]:550 Asic[36]:550 Asic[37]:550 Asic[38]:550 Asic[39]:550 Asic[40]:550 
Asic[41]:550 Asic[42]:550 Asic[43]:550 Asic[44]:550 Asic[45]:550 Asic[46]:550 Asic[47]:550 Asic[48]:550 
Asic[49]:550 Asic[50]:550 Asic[51]:550 Asic[52]:550 Asic[53]:550 Asic[54]:550 Asic[55]:550 Asic[56]:550 
Asic[57]:550 Asic[58]:550 Asic[59]:550 Asic[60]:550 Asic[61]:550 Asic[62]:550 
Chain:3 max freq=550
Chain:3 min freq=550

max freq = 550
Chain[J1] PIC temp offset=62,-79,0,0,0,0,0,0
Chain[J1] chip[244] use PIC middle temp offset=-79 typeID=1a
Chain[J3] PIC temp offset=62,-65,0,0,0,0,0,0
Chain[J3] chip[244] use PIC middle temp offset=-65 typeID=1a
Warning: Chain[J3] use PIC temp offset local=29 > middle=32, need calculate offset ...!
Chain[2] chip[244] local:30 remote:25 offset:-65 
Chain[2] chip[244] local:29 remote:30 offset:-66 
Chain[2] chip[244] local:28 remote:31 offset:-69 
Chain[2] chip[244] local:29 remote:27 offset:-67 
Chain[2] chip[244] local:29 remote:30 offset:-68 
Chain[2] chip[244] local:29 remote:28 offset:-67 
Chain[2] chip[244] local:29 remote:30 offset:-68 
Chain[2] chip[244] local:29 remote:28 offset:-67 
Chain[2] chip[244] local:28 remote:31 offset:-70 
Chain[2] chip[244] local:28 remote:27 offset:-69 
Chain[2] chip[244] local:28 remote:27 offset:-68 
Chain[2] chip[244] local:28 remote:29 offset:-69 
Chain[2] chip[244] local:28 remote:27 offset:-68 
Chain[2] chip[244] local:28 remote:28 offset:-68 
Chain[2] chip[244] local:27 remote:32 offset:-73 
Chain[2] chip[244] local:28 remote:25 offset:-70 
Chain[2] chip[244] local:27 remote:26 offset:-69 
Chain[2] chip[244] local:28 remote:27 offset:-68 
Chain[J3] chip[244] get middle temp offset=-68 typeID=1a
Chain[J4] PIC temp offset=62,-85,0,0,0,0,0,0
Chain[J4] chip[244] use PIC middle temp offset=-85 typeID=1a
Warning: Chain[J4] use PIC temp offset local=28 > middle=18, need calculate offset ...!
Chain[3] chip[244] local:32 remote:33 offset:-71 
Chain[3] chip[244] local:31 remote:32 offset:-72 
Chain[3] chip[244] local:32 remote:31 offset:-71 
Chain[3] chip[244] local:31 remote:32 offset:-72 
Chain[3] chip[244] local:32 remote:31 offset:-71 
Chain[3] chip[244] local:32 remote:32 offset:-71 
Chain[3] chip[244] local:31 remote:32 offset:-72 
Chain[3] chip[244] local:31 remote:30 offset:-71 
Chain[3] chip[244] local:30 remote:31 offset:-72 
Chain[3] chip[244] local:30 remote:31 offset:-73 
Chain[3] chip[244] local:31 remote:30 offset:-72 
Chain[3] chip[244] local:30 remote:33 offset:-75 
Chain[3] chip[244] local:31 remote:28 offset:-72 
Chain[3] chip[244] local:31 remote:31 offset:-72 
Chain[3] chip[244] local:30 remote:30 offset:-72 
Chain[3] chip[244] local:29 remote:31 offset:-74 
Chain[3] chip[244] local:31 remote:29 offset:-72 
Chain[3] chip[244] local:31 remote:30 offset:-71 
Chain[J4] chip[244] get middle temp offset=-71 typeID=1a
Chain[J1] set working voltage=940 [6]
Chain[J3] set working voltage=940 [6]
Chain[J4] set working voltage=940 [6]
prepare send works thread on chain[0]
prepare send works thread on chain[1]
prepare send works thread on chain[2]
prepare send works thread on chain[3]
prepare send works thread on chain[4]
prepare send works thread on chain[5]
prepare send works thread on chain[6]
prepare send works thread on chain[7]
prepare send works thread on chain[8]
prepare send works thread on chain[9]
prepare send works thread on chain[10]
prepare send works thread on chain[11]
prepare send works thread on chain[12]
prepare send works thread on chain[13]
prepare send works thread on chain[14]
prepare send works thread on chain[15]
do heat board 8xPatten for 1 times
Find hashboard on Chain[0]
Find hashboard on Chain[2]
Find hashboard on Chain[3]
Check voltage total rate=11850
get PIC voltage=940 on chain[0], check: must be < 940
get PIC voltage=940 on chain[2], check: must be < 940
get PIC voltage=940 on chain[3], check: must be < 940
start send works on chain[0]
start send works on chain[2]
start send works on chain[3]
wait send works done on chain[0]
get send work num :57456 on Chain[2]
get send work num :57456 on Chain[0]
get send work num :57456 on Chain[3]
wait send works done on chain[2]
wait send works done on chain[3]
wait recv nonce on chain[0]
wait recv nonce on chain[2]
wait recv nonce on chain[3]
get nonces on chain[0]
require nonce number:912
require validnonce number:57456
asic[00]=912	asic[01]=912	asic[02]=912	asic[03]=912	asic[04]=912	asic[05]=912	asic[06]=912	asic[07]=912	
asic[08]=00	asic[09]=912	asic[10]=912	asic[11]=912	asic[12]=912	asic[13]=912	asic[14]=912	asic[15]=912	
asic[16]=912	asic[17]=912	asic[18]=912	asic[19]=912	asic[20]=912	asic[21]=912	asic[22]=912	asic[23]=912	
asic[24]=912	asic[25]=912	asic[26]=912	asic[27]=912	asic[28]=912	asic[29]=912	asic[30]=912	asic[31]=912	
asic[32]=912	asic[33]=912	asic[34]=912	asic[35]=912	asic[36]=912	asic[37]=912	asic[38]=912	asic[39]=912	
asic[40]=912	asic[41]=00	asic[42]=912	asic[43]=911	asic[44]=912	asic[45]=912	asic[46]=912	asic[47]=912	
asic[48]=912	asic[49]=912	asic[50]=912	asic[51]=912	asic[52]=912	asic[53]=912	asic[54]=912	asic[55]=912	
asic[56]=912	asic[57]=912	asic[58]=912	asic[59]=912	asic[60]=912	asic[61]=912	asic[62]=911	


Below ASIC's core didn't receive all the nonce, they should receive 8 nonce each!

asic[08]=00
core[000]=0	core[001]=0	core[002]=0	core[003]=0	core[004]=0	core[005]=0	core[006]=0	core[007]=0	core[008]=0	core[009]=0	core[010]=0	core[011]=0	core[012]=0	core[013]=0	core[014]=0	core[015]=0	core[016]=0	core[017]=0	core[018]=0	core[019]=0	core[020]=0	core[021]=0	core[022]=0	core[023]=0	core[024]=0	core[025]=0	core[026]=0	core[027]=0	core[028]=0	core[029]=0	core[030]=0	core[031]=0	core[032]=0	core[033]=0	core[034]=0	core[035]=0	core[036]=0	core[037]=0	core[038]=0	core[039]=0	core[040]=0	core[041]=0	core[042]=0	core[043]=0	core[044]=0	core[045]=0	core[046]=0	core[047]=0	core[048]=0	core[049]=0	core[050]=0	core[051]=0	core[052]=0	core[053]=0	core[054]=0	core[055]=0	core[056]=0	core[057]=0	core[058]=0	core[059]=0	core[060]=0	core[061]=0	core[062]=0	core[063]=0	core[064]=0	core[065]=0	core[066]=0	core[067]=0	core[068]=0	core[069]=0	core[070]=0	core[071]=0	core[072]=0	core[073]=0	core[074]=0	core[075]=0	core[076]=0	core[077]=0	core[078]=0	core[079]=0	core[080]=0	core[081]=0	core[082]=0	core[083]=0	core[084]=0	core[085]=0	core[086]=0	core[087]=0	core[088]=0	core[089]=0	core[090]=0	core[091]=0	core[092]=0	core[093]=0	core[094]=0	core[095]=0	core[096]=0	core[097]=0	core[098]=0	core[099]=0	core[100]=0	core[101]=0	core[102]=0	core[103]=0	core[104]=0	core[105]=0	core[106]=0	core[107]=0	core[108]=0	core[109]=0	core[110]=0	core[111]=0	core[112]=0	core[113]=0	

asic[41]=00
core[000]=0	core[001]=0	core[002]=0	core[003]=0	core[004]=0	core[005]=0	core[006]=0	core[007]=0	core[008]=0	core[009]=0	core[010]=0	core[011]=0	core[012]=0	core[013]=0	core[014]=0	core[015]=0	core[016]=0	core[017]=0	core[018]=0	core[019]=0	core[020]=0	core[021]=0	core[022]=0	core[023]=0	core[024]=0	core[025]=0	core[026]=0	core[027]=0	core[028]=0	core[029]=0	core[030]=0	core[031]=0	core[032]=0	core[033]=0	core[034]=0	core[035]=0	core[036]=0	core[037]=0	core[038]=0	core[039]=0	core[040]=0	core[041]=0	core[042]=0	core[043]=0	core[044]=0	core[045]=0	core[046]=0	core[047]=0	core[048]=0	core[049]=0	core[050]=0	core[051]=0	core[052]=0	core[053]=0	core[054]=0	core[055]=0	core[056]=0	core[057]=0	core[058]=0	core[059]=0	core[060]=0	core[061]=0	core[062]=0	core[063]=0	core[064]=0	core[065]=0	core[066]=0	core[067]=0	core[068]=0	core[069]=0	core[070]=0	core[071]=0	core[072]=0	core[073]=0	core[074]=0	core[075]=0	core[076]=0	core[077]=0	core[078]=0	core[079]=0	core[080]=0	core[081]=0	core[082]=0	core[083]=0	core[084]=0	core[085]=0	core[086]=0	core[087]=0	core[088]=0	core[089]=0	core[090]=0	core[091]=0	core[092]=0	core[093]=0	core[094]=0	core[095]=0	core[096]=0	core[097]=0	core[098]=0	core[099]=0	core[100]=0	core[101]=0	core[102]=0	core[103]=0	core[104]=0	core[105]=0	core[106]=0	core[107]=0	core[108]=0	core[109]=0	core[110]=0	core[111]=0	core[112]=0	core[113]=0	

asic[43]=911
core[049]=7	

asic[62]=911
core[053]=7	



freq[00]=550	freq[01]=550	freq[02]=550	freq[03]=550	freq[04]=550	freq[05]=550	freq[06]=550	freq[07]=550	
freq[08]=550	freq[09]=550	freq[10]=550	freq[11]=550	freq[12]=550	freq[13]=550	freq[14]=550	freq[15]=550	
freq[16]=550	freq[17]=550	freq[18]=550	freq[19]=550	freq[20]=550	freq[21]=550	freq[22]=550	freq[23]=550	
freq[24]=550	freq[25]=550	freq[26]=550	freq[27]=550	freq[28]=550	freq[29]=550	freq[30]=550	freq[31]=550	
freq[32]=550	freq[33]=550	freq[34]=550	freq[35]=550	freq[36]=550	freq[37]=550	freq[38]=550	freq[39]=550	
freq[40]=550	freq[41]=550	freq[42]=550	freq[43]=550	freq[44]=550	freq[45]=550	freq[46]=550	freq[47]=550	
freq[48]=550	freq[49]=550	freq[50]=550	freq[51]=550	freq[52]=550	freq[53]=550	freq[54]=550	freq[55]=550	
freq[56]=550	freq[57]=550	freq[58]=550	freq[59]=550	freq[60]=550	freq[61]=550	freq[62]=550	

total valid nonce number:55630
total send work number:57456
require valid nonce number:57456
repeated_nonce_num:83
err_nonce_num:43692
last_nonce_num:1071
get nonces on chain[2]
require nonce number:912
require validnonce number:57456
asic[00]=912	asic[01]=912	asic[02]=912	asic[03]=912	asic[04]=912	asic[05]=912	asic[06]=912	asic[07]=912	
asic[08]=912	asic[09]=912	asic[10]=912	asic[11]=912	asic[12]=912	asic[13]=912	asic[14]=912	asic[15]=911	
asic[16]=912	asic[17]=912	asic[18]=912	asic[19]=912	asic[20]=912	asic[21]=912	asic[22]=911	asic[23]=912	
asic[24]=912	asic[25]=912	asic[26]=912	asic[27]=912	asic[28]=912	asic[29]=912	asic[30]=912	asic[31]=912	
asic[32]=912	asic[33]=912	asic[34]=912	asic[35]=912	asic[36]=912	asic[37]=912	asic[38]=912	asic[39]=912	
asic[40]=912	asic[41]=912	asic[42]=912	asic[43]=912	asic[44]=912	asic[45]=912	asic[46]=912	asic[47]=912	
asic[48]=912	asic[49]=912	asic[50]=912	asic[51]=912	asic[52]=912	asic[53]=912	asic[54]=912	asic[55]=912	
asic[56]=912	asic[57]=912	asic[58]=912	asic[59]=912	asic[60]=912	asic[61]=912	asic[62]=912	


Below ASIC's core didn't receive all the nonce, they should receive 8 nonce each!

asic[15]=911
core[043]=7	

asic[22]=911
core[045]=7	



freq[00]=550	freq[01]=550	freq[02]=550	freq[03]=550	freq[04]=550	freq[05]=550	freq[06]=550	freq[07]=550	
freq[08]=550	freq[09]=550	freq[10]=550	freq[11]=550	freq[12]=550	freq[13]=550	freq[14]=550	freq[15]=550	
freq[16]=550	freq[17]=550	freq[18]=550	freq[19]=550	freq[20]=550	freq[21]=550	freq[22]=550	freq[23]=550	
freq[24]=550	freq[25]=550	freq[26]=550	freq[27]=550	freq[28]=550	freq[29]=550	freq[30]=550	freq[31]=550	
freq[32]=550	freq[33]=550	freq[34]=550	freq[35]=550	freq[36]=550	freq[37]=550	freq[38]=550	freq[39]=550	
freq[40]=550	freq[41]=550	freq[42]=550	freq[43]=550	freq[44]=550	freq[45]=550	freq[46]=550	freq[47]=550	
freq[48]=550	freq[49]=550	freq[50]=550	freq[51]=550	freq[52]=550	freq[53]=550	freq[54]=550	freq[55]=550	
freq[56]=550	freq[57]=550	freq[58]=550	freq[59]=550	freq[60]=550	freq[61]=550	freq[62]=550	

total valid nonce number:57454
total send work number:57456
require valid nonce number:57456
repeated_nonce_num:303
err_nonce_num:45692
last_nonce_num:827
get nonces on chain[3]
require nonce number:912
require validnonce number:57456
asic[00]=912	asic[01]=912	asic[02]=912	asic[03]=912	asic[04]=912	asic[05]=912	asic[06]=912	asic[07]=912	
asic[08]=912	asic[09]=912	asic[10]=912	asic[11]=912	asic[12]=912	asic[13]=912	asic[14]=912	asic[15]=912	
asic[16]=912	asic[17]=912	asic[18]=912	asic[19]=912	asic[20]=912	asic[21]=912	asic[22]=912	asic[23]=912	
asic[24]=912	asic[25]=912	asic[26]=912	asic[27]=912	asic[28]=912	asic[29]=911	asic[30]=912	asic[31]=912	
asic[32]=912	asic[33]=912	asic[34]=912	asic[35]=912	asic[36]=912	asic[37]=912	asic[38]=912	asic[39]=912	
asic[40]=912	asic[41]=912	asic[42]=912	asic[43]=912	asic[44]=912	asic[45]=912	asic[46]=911	asic[47]=912	
asic[48]=912	asic[49]=912	asic[50]=912	asic[51]=912	asic[52]=912	asic[53]=912	asic[54]=912	asic[55]=912	
asic[56]=912	asic[57]=912	asic[58]=912	asic[59]=912	asic[60]=912	asic[61]=912	asic[62]=912	


Below ASIC's core didn't receive all the nonce, they should receive 8 nonce each!

asic[29]=911
core[105]=7	

asic[46]=911
core[107]=7	



freq[00]=550	freq[01]=550	freq[02]=550	freq[03]=550	freq[04]=550	freq[05]=550	freq[06]=550	freq[07]=550	
freq[08]=550	freq[09]=550	freq[10]=550	freq[11]=550	freq[12]=550	freq[13]=550	freq[14]=550	freq[15]=550	
freq[16]=550	freq[17]=550	freq[18]=550	freq[19]=550	freq[20]=550	freq[21]=550	freq[22]=550	freq[23]=550	
freq[24]=550	freq[25]=550	freq[26]=550	freq[27]=550	freq[28]=550	freq[29]=550	freq[30]=550	freq[31]=550	
freq[32]=550	freq[33]=550	freq[34]=550	freq[35]=550	freq[36]=550	freq[37]=550	freq[38]=550	freq[39]=550	
freq[40]=550	freq[41]=550	freq[42]=550	freq[43]=550	freq[44]=550	freq[45]=550	freq[46]=550	freq[47]=550	
freq[48]=550	freq[49]=550	freq[50]=550	freq[51]=550	freq[52]=550	freq[53]=550	freq[54]=550	freq[55]=550	
freq[56]=550	freq[57]=550	freq[58]=550	freq[59]=550	freq[60]=550	freq[61]=550	freq[62]=550	

total valid nonce number:57454
total send work number:57456
require valid nonce number:57456
repeated_nonce_num:242
err_nonce_num:45571
last_nonce_num:825
chain[0]: some chip cores are not opened FAILED!
Test Patten on chain[0]: FAILED!
Try to add voltage on chain[0]...
chain[2]: All chip cores are opened OK!
Test Patten on chain[2]: FAILED!
Try to add voltage on chain[2]...
chain[3]: All chip cores are opened OK!
Test Patten on chain[3]: FAILED!
Try to add voltage on chain[3]...
do heat board 8xPatten for 2 times
Find hashboard on Chain[0]
Find hashboard on Chain[2]
Find hashboard on Chain[3]
Check voltage total rate=11850
get PIC voltage=940 on chain[0], check: must be < 940
get PIC voltage=940 on chain[2], check: must be < 940
get PIC voltage=940 on chain[3], check: must be < 940
do open core on Chain[0]...
Done open core on Chain[0]!
start send works on chain[0]
start send works on chain[2]
start send works on chain[3]
wait send works done on chain[0]
get send work num :57456 on Chain[3]
get send work num :57456 on Chain[2]
get send work num :57456 on Chain[0]
wait send works done on chain[2]
wait send works done on chain[3]
wait recv nonce on chain[0]
wait recv nonce on chain[2]
wait recv nonce on chain[3]
get nonces on chain[0]
BitMaxz
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Activity: 3430
Merit: 3168


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April 10, 2022, 11:12:38 PM
 #2
Are you sure about the unit model is it an Antminer s9? Or a clone one?

The kernel logs are a bit different compared to my Antminer s9 I don't know for the C5 controller but would you mind to try to flash it through the SD card?

You can follow the guide from this link below

- https://support.bitmain.com/hc/en-us/articles/360019493654-S9-series-S9-S9i-S9j-S9-Hydro-Control-Board-Program-Recovery
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dacoin305 (OP)
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Activity: 4
Merit: 0


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April 11, 2022, 03:20:01 AM
 #3
Quote from: BitMaxz on April 10, 2022, 11:12:38 PM
Are you sure about the unit model is it an Antminer s9? Or a clone one?

The kernel logs are a bit different compared to my Antminer s9 I don't know for the C5 controller but would you mind to try to flash it through the SD card?

You can follow the guide from this link below

- https://support.bitmain.com/hc/en-us/articles/360019493654-S9-series-S9-S9i-S9j-S9-Hydro-Control-Board-Program-Recovery

Its a antminer s9 11.85th
dacoin305 (OP)
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April 12, 2022, 12:20:50 AM
 #4
@bitmaxz every time I try to flash via website it says incorrect file. will it be different if I use sd card?
BitMaxz
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April 12, 2022, 05:02:21 PM
 #5
Quote from: dacoin305 on April 12, 2022, 12:20:50 AM
@bitmaxz every time I try to flash via website it says incorrect file. will it be different if I use sd card?

It will be incorrect file if you are trying to flash SD card image through browser.
You need SD card and put all extracted file to SD card. Follow the guide from the link that I posted above.

Or if your miner control board is c5 then you wont be able to flash it through SD card. Use the firmware with extension tar.gz that support c5 controller and upgrade it through browser.
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dacoin305 (OP)
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April 14, 2022, 05:10:37 AM
 #6
Quote from: BitMaxz on April 12, 2022, 05:02:21 PM
Quote from: dacoin305 on April 12, 2022, 12:20:50 AM
@bitmaxz every time I try to flash via website it says incorrect file. will it be different if I use sd card?

It will be incorrect file if you are trying to flash SD card image through browser.
You need SD card and put all extracted file to SD card. Follow the guide from the link that I posted above.

Or if your miner control board is c5 then you wont be able to flash it through SD card. Use the firmware with extension tar.gz that support c5 controller and upgrade it through browser.


I updated through web browser and the problem is the same. here's the new log

Quote
Booting Linux on physical CPU 0x0
Initializing cgroup subsys cpuset
Linux version 3.10.31-ltsi-00003-gcf03eb9 (lzq@armdev01) (gcc version 4.7.3 20121106 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2012.11-20121123 - Linaro GCC 2012.11) ) #81 SMP Mon Apr 25 11:20:36 CST 2016
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: Altera SOCFPGA, model: Altera SOCFPGA Cyclone V
Memory policy: ECC disabled, Data cache writealloc
On node 0 totalpages: 258048
free_area_init_node: node 0, pgdat 806e5cc0, node_mem_map 8072a000
  Normal zone: 2016 pages used for memmap
  Normal zone: 0 pages reserved
  Normal zone: 258048 pages, LIFO batch:31
PERCPU: Embedded 8 pages/cpu @80f17000 s11200 r8192 d13376 u32768
pcpu-alloc: s11200 r8192 d13376 u32768 alloc=8*4096
pcpu-alloc:
  • 0
  • 1
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 256032
Kernel command line: mem=1008M console=ttyS0,115200 root=/dev/mtdblock3 rw rootfstype=jffs2
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 1008MB = 1008MB total
Memory: 1015844k/1015844k available, 16348k reserved, 0K highmem
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
    vmalloc : 0xbf800000 - 0xff000000   (1016 MB)
    lowmem  : 0x80000000 - 0xbf000000   (1008 MB)
    modules : 0x7f000000 - 0x80000000   (  16 MB)
      .text : 0x80008000 - 0x8065a930   (6475 kB)
      .init : 0x8065b000 - 0x806adbc0   ( 331 kB)
      .data : 0x806ae000 - 0x806e9990   ( 239 kB)
       .bss : 0x806e9990 - 0x80729384   ( 255 kB)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
Hierarchical RCU implementation.
NR_IRQS:16 nr_irqs:16 16
sched_clock: 32 bits at 100MHz, resolution 10ns, wraps every 42949ms
Console: colour dummy device 80x30
Calibrating delay loop... 1196.85 BogoMIPS (lpj=5984256)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
ftrace: allocating 17687 entries in 52 pages
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x804ab220 - 0x804ab278
CPU1: failed to come online
Brought up 1 CPUs
SMP: Total of 1 processors activated (1196.85 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
NET: Registered protocol family 16
fpga bridge driver
DMA: preallocated 256 KiB pool for atomic coherent allocations
L310 cache controller enabled
l2x0: 8 ways, CACHE_ID 0x410030c9, AUX_CTRL 0x32460000, Cache size: 524288 B
syscon fffef000.l2-cache: regmap [mem 0xfffef000-0xfffeffff] registered
syscon ffd05000.rstmgr: regmap [mem 0xffd05000-0xffd05fff] registered
syscon ffc25000.sdrctl: regmap [mem 0xffc25000-0xffc25fff] registered
syscon ff800000.l3regs: regmap [mem 0xff800000-0xff800fff] registered
syscon ffd08000.sysmgr: regmap [mem 0xffd08000-0xffd0bfff] registered
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
altera_hps2fpga_bridge fpgabridge.2: fpga bridge [hps2fpga] registered as device hps2fpga
altera_hps2fpga_bridge fpgabridge.2: init-val not specified
altera_hps2fpga_bridge fpgabridge.3: fpga bridge [lshps2fpga] registered as device lwhps2fpga
altera_hps2fpga_bridge fpgabridge.3: init-val not specified
altera_hps2fpga_bridge fpgabridge.4: fpga bridge [fpga2hps] registered as device fpga2hps
altera_hps2fpga_bridge fpgabridge.4: init-val not specified
bio: create slab <bio-0> at 0
FPGA Mangager framework driver
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
Switching to clocksource timer0
NET: Registered protocol family 2
TCP established hash table entries: 8192 (order: 4, 65536 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
TCP: reno registered
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
arm-pmu arm-pmu: PMU:CTI successfully enabled for 1 cores
NFS: Registering the id_resolver key type
Key type id_resolver registered
Key type id_legacy registered
NTFS driver 2.1.30 [Flags: R/W].
jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
msgmni has been set to 1984
io scheduler noop registered (default)
Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
ffc02000.serial0: ttyS0 at MMIO 0xffc02000 (irq = 194) is a 16550A
console [ttyS0] enabled
altera_fpga_manager ff706000.fpgamgr: fpga manager [Altera FPGA Manager] registered as minor 0
brd: module loaded
denali-nand-dt ff900000.nand: Dump timing register values:acc_clks: 4, re_2_we: 20, re_2_re: 20
we_2_re: 12, addr_2_data: 14, rdwr_en_lo_cnt: 2
rdwr_en_hi_cnt: 2, cs_setup_cnt: 2
ONFI param page 0 valid
ONFI flash detected
NAND device: Manufacturer ID: 0x2c, Chip ID: 0xda (Micron MT29F2G08ABAEAWP), 256MiB, page size: 2048, OOB size: 64
Bad block table found at page 131008, version 0x01
Bad block table found at page 130944, version 0x01
5 ofpart partitions found on MTD device denali-nand
Creating 5 MTD partitions on "denali-nand":
0x000000000000-0x000001000000 : "NAND Flash Boot Area 16MB"
0x000001000000-0x000002000000 : "NAND Flash Boot Area backup1 16MB"
0x000002000000-0x000003000000 : "NAND Flash Boot Area backup2 16MB"
0x000003000000-0x00000b000000 : "NAND Flash jffs2 Root Filesystem 128MB"
0x00000b000000-0x000010000000 : "NAND Flash jffs2 Root Filesystem 80MB"
dw_spi_mmio fff00000.spi: master is unqueued, this is deprecated
CAN device driver interface
c_can_platform ffc00000.d_can: invalid resource
c_can_platform ffc00000.d_can: control memory is not used for raminit
c_can_platform ffc00000.d_can: c_can_platform device registered (regs=bf8dc000, irq=163)
stmmac_hw_init: 1000M
stmmac - user ID: 0x10, Synopsys ID: 0x37
 Ring mode enabled
 DMA HW capability register supported
 Enhanced/Alternate descriptors
   Enabled extended descriptors
 RX Checksum Offload Engine supported (type 2)
 TX Checksum insertion supported
 Enable RX Mitigation via HW Watchdog Timer
libphy: stmmac: probed
eth0: PHY ID 0007c0f1 at 0 IRQ POLL (stmmac-0:00) active
usbcore: registered new interface driver usb-storage
mousedev: PS/2 mouse device common for all mice
i2c /dev entries driver
Synopsys Designware Multimedia Card Interface Driver
dwmmc_socfpga ff704000.dwmmc0: couldn't determine pwr-en, assuming pwr-en = 0
dwmmc_socfpga ff704000.dwmmc0: Using internal DMA controller.
dwmmc_socfpga ff704000.dwmmc0: Version ID is 240a
dwmmc_socfpga ff704000.dwmmc0: DW MMC controller at irq 171, 32 bit host data width, 1024 deep fifo
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
dwmmc_socfpga ff704000.dwmmc0: 1 slots initialized
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
oprofile: using arm/armv7-ca9
TCP: cubic registered
NET: Registered protocol family 10
sit: IPv6 over IPv4 tunneling driver
NET: Registered protocol family 17
NET: Registered protocol family 15
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20120528 t)
can: netlink gateway (rev 20130117) max_hops=1
8021q: 802.1Q VLAN Support v1.8
Key type dns_resolver registered
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
ThumbEE CPU extension supported.
Registering SWP/SWPB emulation handler
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
jffs2: Empty flash at 0x0139ba2c ends at 0x0139c000
VFS: Mounted root (jffs2 filesystem) on device 31:3.
devtmpfs: mounted
Freeing unused kernel memory: 328K (8065b000 - 806ad000)
eth0: device MAC address ae:f6:07:a7:36:08
init phy ok
PHY DMA init OK
eth0: device MAC address 00:91:6b:66:c0:ed
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
libphy: stmmac-0:00 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
In axi fpga driver!
Original value in RESET_MANAGER_BASE_ADDR + BRGMODRST_ADDR is 0x0
request_mem_region OK!
AXI fpga dev virtual address is 0xbf942000
*base_vir_addr = 0xc504
In fpga mem driver!
request_mem_region OK!
fpga mem virtual address is 0xc0000000
eth0: device MAC address 00:91:6b:66:c0:ed
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
eth0: device MAC address 00:91:6b:66:c0:ed
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
libphy: stmmac-0:00 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
prepare send works thread on chain[0]
prepare send works thread on chain[1]
prepare send works thread on chain[2]
prepare send works thread on chain[3]
prepare send works thread on chain[4]
prepare send works thread on chain[5]
prepare send works thread on chain[6]
prepare send works thread on chain[7]
prepare send works thread on chain[8]
prepare send works thread on chain[9]
prepare send works thread on chain[10]
prepare send works thread on chain[11]
prepare send works thread on chain[12]
prepare send works thread on chain[13]
prepare send works thread on chain[14]
prepare send works thread on chain[15]
Find hashboard on Chain[0]
Find hashboard on Chain[2]
Find hashboard on Chain[3]
Check chain[0] PIC fw version=0x02
Check chain[2] PIC fw version=0x02
Check chain[3] PIC fw version=0x02
chain[0] has no freq in PIC! Will use default freq=550 and jump over...
Check chain[0] PIC fw version=0x02
chain[2] has no freq in PIC! Will use default freq=550 and jump over...
Check chain[2] PIC fw version=0x02
chain[3] has no freq in PIC! Will use default freq=550 and jump over...
Check chain[3] PIC fw version=0x02
set command mode to VIL

singleBoardTest: AsicType = 1387

singleBoardTest: asicNum = 64

singleBoardTest: real AsicNum = 63

--- check asic number
set_baud=1
The min freq=700
set real timeout 52, need sleep=379392
search freq for 1 times, completed chain = 3, total chain num = 3
disable_pic_dac on chain[0]
disable_pic_dac on chain[2]
disable_pic_dac on chain[3]
restart Miner chance num=2
waiting for send_func to exit of chain[0]
waiting for send_func to exit of chain[1]
waiting for send_func to exit of chain[2]
waiting for send_func to exit of chain[3]
waiting for send_func to exit of chain[4]
waiting for send_func to exit of chain[5]
waiting for send_func to exit of chain[6]
waiting for send_func to exit of chain[7]
waiting for send_func to exit of chain[8]
waiting for send_func to exit of chain[9]
waiting for send_func to exit of chain[10]
waiting for send_func to exit of chain[11]
waiting for send_func to exit of chain[12]
waiting for send_func to exit of chain[13]
waiting for send_func to exit of chain[14]
waiting for send_func to exit of chain[15]
waiting for receive_func to exit!
waiting for pic heart to exit!
Start bmminer ...
Check chain[0] PIC fw version=0x02
Check chain[2] PIC fw version=0x02
Check chain[3] PIC fw version=0x02
Chain[J1] chain_voltage=6 value=940
Chain[J3] chain_voltage=6 value=940
Chain[J4] chain_voltage=6 value=940
Chain[J1] has 62 asic
Chain[J3] has 63 asic
Chain[J4] has 63 asic
Chain[J1] has no freq in PIC, set default freq=550M
Chain[J1] has no core num in PIC
Chain[J3] has no freq in PIC, set default freq=550M
Chain[J3] has no core num in PIC
Chain[J4] has no freq in PIC, set default freq=550M
Chain[J4] has no core num in PIC
read PIC voltage=940 on chain[0]
Chain:0 chipnum=62
Chain[J1] voltage added=0.0V
Chain[J1] [minerMAC: 00:91:6b:66:c0:ed hashMAC: 00:00:00:00:00:00]
Chain:0 temp offset=0
Chain:0 base freq=100
Asic[ 0]:550
Asic[ 1]:550 Asic[ 2]:550 Asic[ 3]:550 Asic[ 4]:550 Asic[ 5]:550 Asic[ 6]:550 Asic[ 7]:550 Asic[ 8]:550
Asic[ 9]:550 Asic[10]:550 Asic[11]:550 Asic[12]:550 Asic[13]:550 Asic[14]:550 Asic[15]:550 Asic[16]:550
Asic[17]:550 Asic[18]:550 Asic[19]:550 Asic[20]:550 Asic[21]:550 Asic[22]:550 Asic[23]:550 Asic[24]:550
Asic[25]:550 Asic[26]:550 Asic[27]:550 Asic[28]:550 Asic[29]:550 Asic[30]:550 Asic[31]:550 Asic[32]:550
Asic[33]:550 Asic[34]:550 Asic[35]:550 Asic[36]:550 Asic[37]:550 Asic[38]:550 Asic[39]:550 Asic[40]:550
Asic[41]:550 Asic[42]:550 Asic[43]:550 Asic[44]:550 Asic[45]:550 Asic[46]:550 Asic[47]:550 Asic[48]:550
Asic[49]:550 Asic[50]:550 Asic[51]:550 Asic[52]:550 Asic[53]:550 Asic[54]:550 Asic[55]:550 Asic[56]:550
Asic[57]:550 Asic[58]:550 Asic[59]:550 Asic[60]:550 Asic[61]:550
Chain:0 max freq=550
Chain:0 min freq=550

read PIC voltage=940 on chain[2]
Chain:2 chipnum=63
Chain[J3] voltage added=0.0V
Chain[J3] [minerMAC: 00:91:6b:66:c0:ed hashMAC: 00:00:00:00:00:00]
Chain:2 temp offset=0
Chain:2 base freq=100
Asic[ 0]:550
Asic[ 1]:550 Asic[ 2]:550 Asic[ 3]:550 Asic[ 4]:550 Asic[ 5]:550 Asic[ 6]:550 Asic[ 7]:550 Asic[ 8]:550
Asic[ 9]:550 Asic[10]:550 Asic[11]:550 Asic[12]:550 Asic[13]:550 Asic[14]:550 Asic[15]:550 Asic[16]:550
Asic[17]:550 Asic[18]:550 Asic[19]:550 Asic[20]:550 Asic[21]:550 Asic[22]:550 Asic[23]:550 Asic[24]:550
Asic[25]:550 Asic[26]:550 Asic[27]:550 Asic[28]:550 Asic[29]:550 Asic[30]:550 Asic[31]:550 Asic[32]:550
Asic[33]:550 Asic[34]:550 Asic[35]:550 Asic[36]:550 Asic[37]:550 Asic[38]:550 Asic[39]:550 Asic[40]:550
Asic[41]:550 Asic[42]:550 Asic[43]:550 Asic[44]:550 Asic[45]:550 Asic[46]:550 Asic[47]:550 Asic[48]:550
Asic[49]:550 Asic[50]:550 Asic[51]:550 Asic[52]:550 Asic[53]:550 Asic[54]:550 Asic[55]:550 Asic[56]:550
Asic[57]:550 Asic[58]:550 Asic[59]:550 Asic[60]:550 Asic[61]:550 Asic[62]:550
Chain:2 max freq=550
Chain:2 min freq=550

read PIC voltage=940 on chain[3]
Chain:3 chipnum=63
Chain[J4] voltage added=0.0V
Chain[J4] [minerMAC: 00:91:6b:66:c0:ed hashMAC: 00:00:00:00:00:00]
Chain:3 temp offset=0
Chain:3 base freq=100
Asic[ 0]:550
Asic[ 1]:550 Asic[ 2]:550 Asic[ 3]:550 Asic[ 4]:550 Asic[ 5]:550 Asic[ 6]:550 Asic[ 7]:550 Asic[ 8]:550
Asic[ 9]:550 Asic[10]:550 Asic[11]:550 Asic[12]:550 Asic[13]:550 Asic[14]:550 Asic[15]:550 Asic[16]:550
Asic[17]:550 Asic[18]:550 Asic[19]:550 Asic[20]:550 Asic[21]:550 Asic[22]:550 Asic[23]:550 Asic[24]:550
Asic[25]:550 Asic[26]:550 Asic[27]:550 Asic[28]:550 Asic[29]:550 Asic[30]:550 Asic[31]:550 Asic[32]:550
Asic[33]:550 Asic[34]:550 Asic[35]:550 Asic[36]:550 Asic[37]:550 Asic[38]:550 Asic[39]:550 Asic[40]:550
Asic[41]:550 Asic[42]:550 Asic[43]:550 Asic[44]:550 Asic[45]:550 Asic[46]:550 Asic[47]:550 Asic[48]:550
Asic[49]:550 Asic[50]:550 Asic[51]:550 Asic[52]:550 Asic[53]:550 Asic[54]:550 Asic[55]:550 Asic[56]:550
Asic[57]:550 Asic[58]:550 Asic[59]:550 Asic[60]:550 Asic[61]:550 Asic[62]:550
Chain:3 max freq=550
Chain:3 min freq=550


Miner fix freq ...
read PIC voltage=940 on chain[0]
Chain:0 chipnum=62
Chain[J1] voltage added=0.0V
Chain[J1] [minerMAC: 00:91:6b:66:c0:ed hashMAC: 00:00:00:00:00:00]
Chain:0 temp offset=0
Chain:0 base freq=100
Asic[ 0]:550
Asic[ 1]:550 Asic[ 2]:550 Asic[ 3]:550 Asic[ 4]:550 Asic[ 5]:550 Asic[ 6]:550 Asic[ 7]:550 Asic[ 8]:550
Asic[ 9]:550 Asic[10]:550 Asic[11]:550 Asic[12]:550 Asic[13]:550 Asic[14]:550 Asic[15]:550 Asic[16]:550
Asic[17]:550 Asic[18]:550 Asic[19]:550 Asic[20]:550 Asic[21]:550 Asic[22]:550 Asic[23]:550 Asic[24]:550
Asic[25]:550 Asic[26]:550 Asic[27]:550 Asic[28]:550 Asic[29]:550 Asic[30]:550 Asic[31]:550 Asic[32]:550
Asic[33]:550 Asic[34]:550 Asic[35]:550 Asic[36]:550 Asic[37]:550 Asic[38]:550 Asic[39]:550 Asic[40]:550
Asic[41]:550 Asic[42]:550 Asic[43]:550 Asic[44]:550 Asic[45]:550 Asic[46]:550 Asic[47]:550 Asic[48]:550
Asic[49]:550 Asic[50]:550 Asic[51]:550 Asic[52]:550 Asic[53]:550 Asic[54]:550 Asic[55]:550 Asic[56]:550
Asic[57]:550 Asic[58]:550 Asic[59]:550 Asic[60]:550 Asic[61]:550
Chain:0 max freq=550
Chain:0 min freq=550

read PIC voltage=940 on chain[2]
Chain:2 chipnum=63
Chain[J3] voltage added=0.0V
Chain[J3] [minerMAC: 00:91:6b:66:c0:ed hashMAC: 00:00:00:00:00:00]
Chain:2 temp offset=0
Chain:2 base freq=100
Asic[ 0]:550
Asic[ 1]:550 Asic[ 2]:550 Asic[ 3]:550 Asic[ 4]:550 Asic[ 5]:550 Asic[ 6]:550 Asic[ 7]:550 Asic[ 8]:550
Asic[ 9]:550 Asic[10]:550 Asic[11]:550 Asic[12]:550 Asic[13]:550 Asic[14]:550 Asic[15]:550 Asic[16]:550
Asic[17]:550 Asic[18]:550 Asic[19]:550 Asic[20]:550 Asic[21]:550 Asic[22]:550 Asic[23]:550 Asic[24]:550
Asic[25]:550 Asic[26]:550 Asic[27]:550 Asic[28]:550 Asic[29]:550 Asic[30]:550 Asic[31]:550 Asic[32]:550
Asic[33]:550 Asic[34]:550 Asic[35]:550 Asic[36]:550 Asic[37]:550 Asic[38]:550 Asic[39]:550 Asic[40]:550
Asic[41]:550 Asic[42]:550 Asic[43]:550 Asic[44]:550 Asic[45]:550 Asic[46]:550 Asic[47]:550 Asic[48]:550
Asic[49]:550 Asic[50]:550 Asic[51]:550 Asic[52]:550 Asic[53]:550 Asic[54]:550 Asic[55]:550 Asic[56]:550
Asic[57]:550 Asic[58]:550 Asic[59]:550 Asic[60]:550 Asic[61]:550 Asic[62]:550
Chain:2 max freq=550
Chain:2 min freq=550

read PIC voltage=940 on chain[3]
Chain:3 chipnum=63
Chain[J4] voltage added=0.0V
Chain[J4] [minerMAC: 00:91:6b:66:c0:ed hashMAC: 00:00:00:00:00:00]
Chain:3 temp offset=0
Chain:3 base freq=100
Asic[ 0]:550
Asic[ 1]:550 Asic[ 2]:550 Asic[ 3]:550 Asic[ 4]:550 Asic[ 5]:550 Asic[ 6]:550 Asic[ 7]:550 Asic[ 8]:550
Asic[ 9]:550 Asic[10]:550 Asic[11]:550 Asic[12]:550 Asic[13]:550 Asic[14]:550 Asic[15]:550 Asic[16]:550
Asic[17]:550 Asic[18]:550 Asic[19]:550 Asic[20]:550 Asic[21]:550 Asic[22]:550 Asic[23]:550 Asic[24]:550
Asic[25]:550 Asic[26]:550 Asic[27]:550 Asic[28]:550 Asic[29]:550 Asic[30]:550 Asic[31]:550 Asic[32]:550
Asic[33]:550 Asic[34]:550 Asic[35]:550 Asic[36]:550 Asic[37]:550 Asic[38]:550 Asic[39]:550 Asic[40]:550
Asic[41]:550 Asic[42]:550 Asic[43]:550 Asic[44]:550 Asic[45]:550 Asic[46]:550 Asic[47]:550 Asic[48]:550
Asic[49]:550 Asic[50]:550 Asic[51]:550 Asic[52]:550 Asic[53]:550 Asic[54]:550 Asic[55]:550 Asic[56]:550
Asic[57]:550 Asic[58]:550 Asic[59]:550 Asic[60]:550 Asic[61]:550 Asic[62]:550
Chain:3 max freq=550
Chain:3 min freq=550

max freq = 550
prepare send works thread on chain[0]
prepare send works thread on chain[1]
prepare send works thread on chain[2]
prepare send works thread on chain[3]
prepare send works thread on chain[4]
prepare send works thread on chain[5]
prepare send works thread on chain[6]
prepare send works thread on chain[7]
prepare send works thread on chain[8]
prepare send works thread on chain[9]
prepare send works thread on chain[10]
prepare send works thread on chain[11]
prepare send works thread on chain[12]
prepare send works thread on chain[13]
prepare send works thread on chain[14]
prepare send works thread on chain[15]
Find hashboard on Chain[0]
Find hashboard on Chain[2]
Find hashboard on Chain[3]
use PIC voltage=940 on chain[0]
now set pic voltage=6 on chain[0]
use PIC voltage=940 on chain[2]
now set pic voltage=6 on chain[2]
use PIC voltage=940 on chain[3]
now set pic voltage=6 on chain[3]
enable_pic_dac on chain[0]
enable_pic_dac on chain[2]
enable_pic_dac on chain[3]
do 12 8xPatten test for 1 times
set command mode to VIL

initFpgaBoard: AsicType = 1387

initFpgaBoard: asicNum = 64

initFpgaBoard: real AsicNum = 63

--- check asic number
check chain[0]: asicNum = 63
check chain[2]: asicNum = 63
check chain[3]: asicNum = 63
Set Freq of PIC for Test Patten on Chain[0]
BitMaxz
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April 14, 2022, 04:28:28 PM
 #7
I can't see any issue on the logs or possible errors.
Can you try to flash it again with different firmware available on bitmain(lower version) then try again.

Also, check your router and maybe the firewall is blocking your miner from connecting to the pool.
Also, try to mine on different pools to test. You can check other pools from here https://miningpoolstats.stream/
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April 21, 2022, 10:47:17 AM
Last edit: April 22, 2022, 01:49:58 AM by tornado_blade
 #8
Quote from: dacoin305 on April 14, 2022, 05:10:37 AM
Quote from: BitMaxz on April 12, 2022, 05:02:21 PM
Quote from: dacoin305 on April 12, 2022, 12:20:50 AM
@bitmaxz every time I try to flash via website it says incorrect file. will it be different if I use sd card?

It will be incorrect file if you are trying to flash SD card image through browser.
You need SD card and put all extracted file to SD card. Follow the guide from the link that I posted above.

Or if your miner control board is c5 then you wont be able to flash it through SD card. Use the firmware with extension tar.gz that support c5 controller and upgrade it through browser.


I updated through web browser and the problem is the same. here's the new log

Quote
Booting Linux on physical CPU 0x0
Initializing cgroup subsys cpuset
Linux version 3.10.31-ltsi-00003-gcf03eb9 (lzq@armdev01) (gcc version 4.7.3 20121106 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2012.11-20121123 - Linaro GCC 2012.11) ) #81 SMP Mon Apr 25 11:20:36 CST 2016
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: Altera SOCFPGA, model: Altera SOCFPGA Cyclone V
Memory policy: ECC disabled, Data cache writealloc
On node 0 totalpages: 258048
free_area_init_node: node 0, pgdat 806e5cc0, node_mem_map 8072a000
  Normal zone: 2016 pages used for memmap
  Normal zone: 0 pages reserved
  Normal zone: 258048 pages, LIFO batch:31
PERCPU: Embedded 8 pages/cpu @80f17000 s11200 r8192 d13376 u32768
pcpu-alloc: s11200 r8192 d13376 u32768 alloc=8*4096
pcpu-alloc:
  • 0
  • 1
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 256032
Kernel command line: mem=1008M console=ttyS0,115200 root=/dev/mtdblock3 rw rootfstype=jffs2
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 1008MB = 1008MB total
Memory: 1015844k/1015844k available, 16348k reserved, 0K highmem
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
    vmalloc : 0xbf800000 - 0xff000000   (1016 MB)
    lowmem  : 0x80000000 - 0xbf000000   (1008 MB)
    modules : 0x7f000000 - 0x80000000   (  16 MB)
      .text : 0x80008000 - 0x8065a930   (6475 kB)
      .init : 0x8065b000 - 0x806adbc0   ( 331 kB)
      .data : 0x806ae000 - 0x806e9990   ( 239 kB)
       .bss : 0x806e9990 - 0x80729384   ( 255 kB)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
Hierarchical RCU implementation.
NR_IRQS:16 nr_irqs:16 16
sched_clock: 32 bits at 100MHz, resolution 10ns, wraps every 42949ms
Console: colour dummy device 80x30
Calibrating delay loop... 1196.85 BogoMIPS (lpj=5984256)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
ftrace: allocating 17687 entries in 52 pages
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x804ab220 - 0x804ab278
CPU1: failed to come online
Brought up 1 CPUs
SMP: Total of 1 processors activated (1196.85 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
NET: Registered protocol family 16
fpga bridge driver
DMA: preallocated 256 KiB pool for atomic coherent allocations
L310 cache controller enabled
l2x0: 8 ways, CACHE_ID 0x410030c9, AUX_CTRL 0x32460000, Cache size: 524288 B
syscon fffef000.l2-cache: regmap [mem 0xfffef000-0xfffeffff] registered
syscon ffd05000.rstmgr: regmap [mem 0xffd05000-0xffd05fff] registered
syscon ffc25000.sdrctl: regmap [mem 0xffc25000-0xffc25fff] registered
syscon ff800000.l3regs: regmap [mem 0xff800000-0xff800fff] registered
syscon ffd08000.sysmgr: regmap [mem 0xffd08000-0xffd0bfff] registered
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
altera_hps2fpga_bridge fpgabridge.2: fpga bridge [hps2fpga] registered as device hps2fpga
altera_hps2fpga_bridge fpgabridge.2: init-val not specified
altera_hps2fpga_bridge fpgabridge.3: fpga bridge [lshps2fpga] registered as device lwhps2fpga
altera_hps2fpga_bridge fpgabridge.3: init-val not specified
altera_hps2fpga_bridge fpgabridge.4: fpga bridge [fpga2hps] registered as device fpga2hps
altera_hps2fpga_bridge fpgabridge.4: init-val not specified
bio: create slab <bio-0> at 0
FPGA Mangager framework driver
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
Switching to clocksource timer0
NET: Registered protocol family 2
TCP established hash table entries: 8192 (order: 4, 65536 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
TCP: reno registered
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
arm-pmu arm-pmu: PMU:CTI successfully enabled for 1 cores
NFS: Registering the id_resolver key type
Key type id_resolver registered
Key type id_legacy registered
NTFS driver 2.1.30 [Flags: R/W].
jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
msgmni has been set to 1984
io scheduler noop registered (default)
Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
ffc02000.serial0: ttyS0 at MMIO 0xffc02000 (irq = 194) is a 16550A
console [ttyS0] enabled
altera_fpga_manager ff706000.fpgamgr: fpga manager [Altera FPGA Manager] registered as minor 0
brd: module loaded
denali-nand-dt ff900000.nand: Dump timing register values:acc_clks: 4, re_2_we: 20, re_2_re: 20
we_2_re: 12, addr_2_data: 14, rdwr_en_lo_cnt: 2
rdwr_en_hi_cnt: 2, cs_setup_cnt: 2
ONFI param page 0 valid
ONFI flash detected
NAND device: Manufacturer ID: 0x2c, Chip ID: 0xda (Micron MT29F2G08ABAEAWP), 256MiB, page size: 2048, OOB size: 64
Bad block table found at page 131008, version 0x01
Bad block table found at page 130944, version 0x01
5 ofpart partitions found on MTD device denali-nand
Creating 5 MTD partitions on "denali-nand":
0x000000000000-0x000001000000 : "NAND Flash Boot Area 16MB"
0x000001000000-0x000002000000 : "NAND Flash Boot Area backup1 16MB"
0x000002000000-0x000003000000 : "NAND Flash Boot Area backup2 16MB"
0x000003000000-0x00000b000000 : "NAND Flash jffs2 Root Filesystem 128MB"
0x00000b000000-0x000010000000 : "NAND Flash jffs2 Root Filesystem 80MB"
dw_spi_mmio fff00000.spi: master is unqueued, this is deprecated
CAN device driver interface
c_can_platform ffc00000.d_can: invalid resource
c_can_platform ffc00000.d_can: control memory is not used for raminit
c_can_platform ffc00000.d_can: c_can_platform device registered (regs=bf8dc000, irq=163)
stmmac_hw_init: 1000M
stmmac - user ID: 0x10, Synopsys ID: 0x37
 Ring mode enabled
 DMA HW capability register supported
 Enhanced/Alternate descriptors
   Enabled extended descriptors
 RX Checksum Offload Engine supported (type 2)
 TX Checksum insertion supported
 Enable RX Mitigation via HW Watchdog Timer
libphy: stmmac: probed
eth0: PHY ID 0007c0f1 at 0 IRQ POLL (stmmac-0:00) active
usbcore: registered new interface driver usb-storage
mousedev: PS/2 mouse device common for all mice
i2c /dev entries driver
Synopsys Designware Multimedia Card Interface Driver
dwmmc_socfpga ff704000.dwmmc0: couldn't determine pwr-en, assuming pwr-en = 0
dwmmc_socfpga ff704000.dwmmc0: Using internal DMA controller.
dwmmc_socfpga ff704000.dwmmc0: Version ID is 240a
dwmmc_socfpga ff704000.dwmmc0: DW MMC controller at irq 171, 32 bit host data width, 1024 deep fifo
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
dwmmc_socfpga ff704000.dwmmc0: 1 slots initialized
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
oprofile: using arm/armv7-ca9
TCP: cubic registered
NET: Registered protocol family 10
sit: IPv6 over IPv4 tunneling driver
NET: Registered protocol family 17
NET: Registered protocol family 15
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20120528 t)
can: netlink gateway (rev 20130117) max_hops=1
8021q: 802.1Q VLAN Support v1.8
Key type dns_resolver registered
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
ThumbEE CPU extension supported.
Registering SWP/SWPB emulation handler
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
jffs2: Empty flash at 0x0139ba2c ends at 0x0139c000
VFS: Mounted root (jffs2 filesystem) on device 31:3.
devtmpfs: mounted
Freeing unused kernel memory: 328K (8065b000 - 806ad000)
eth0: device MAC address ae:f6:07:a7:36:08
init phy ok
PHY DMA init OK
eth0: device MAC address 00:91:6b:66:c0:ed
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
libphy: stmmac-0:00 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
In axi fpga driver!
Original value in RESET_MANAGER_BASE_ADDR + BRGMODRST_ADDR is 0x0
request_mem_region OK!
AXI fpga dev virtual address is 0xbf942000
*base_vir_addr = 0xc504
In fpga mem driver!
request_mem_region OK!
fpga mem virtual address is 0xc0000000
eth0: device MAC address 00:91:6b:66:c0:ed
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
eth0: device MAC address 00:91:6b:66:c0:ed
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
libphy: stmmac-0:00 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
prepare send works thread on chain[0]
prepare send works thread on chain[1]
prepare send works thread on chain[2]
prepare send works thread on chain[3]
prepare send works thread on chain[4]
prepare send works thread on chain[5]
prepare send works thread on chain[6]
prepare send works thread on chain[7]
prepare send works thread on chain[8]
prepare send works thread on chain[9]
prepare send works thread on chain[10]
prepare send works thread on chain[11]
prepare send works thread on chain[12]
prepare send works thread on chain[13]
prepare send works thread on chain[14]
prepare send works thread on chain[15]
Find hashboard on Chain[0]
Find hashboard on Chain[2]
Find hashboard on Chain[3]
Check chain[0] PIC fw version=0x02
Check chain[2] PIC fw version=0x02
Check chain[3] PIC fw version=0x02
chain[0] has no freq in PIC! Will use default freq=550 and jump over...
Check chain[0] PIC fw version=0x02
chain[2] has no freq in PIC! Will use default freq=550 and jump over...
Check chain[2] PIC fw version=0x02
chain[3] has no freq in PIC! Will use default freq=550 and jump over...
Check chain[3] PIC fw version=0x02
set command mode to VIL

singleBoardTest: AsicType = 1387

singleBoardTest: asicNum = 64

singleBoardTest: real AsicNum = 63

--- check asic number
set_baud=1
The min freq=700
set real timeout 52, need sleep=379392
search freq for 1 times, completed chain = 3, total chain num = 3
disable_pic_dac on chain[0]
disable_pic_dac on chain[2]
disable_pic_dac on chain[3]
restart Miner chance num=2
waiting for send_func to exit of chain[0]
waiting for send_func to exit of chain[1]
waiting for send_func to exit of chain[2]
waiting for send_func to exit of chain[3]
waiting for send_func to exit of chain[4]
waiting for send_func to exit of chain[5]
waiting for send_func to exit of chain[6]
waiting for send_func to exit of chain[7]
waiting for send_func to exit of chain[8]
waiting for send_func to exit of chain[9]
waiting for send_func to exit of chain[10]
waiting for send_func to exit of chain[11]
waiting for send_func to exit of chain[12]
waiting for send_func to exit of chain[13]
waiting for send_func to exit of chain[14]
waiting for send_func to exit of chain[15]
waiting for receive_func to exit!
waiting for pic heart to exit!
Start bmminer ...
Check chain[0] PIC fw version=0x02
Check chain[2] PIC fw version=0x02
Check chain[3] PIC fw version=0x02
Chain[J1] chain_voltage=6 value=940
Chain[J3] chain_voltage=6 value=940
Chain[J4] chain_voltage=6 value=940
Chain[J1] has 62 asic
Chain[J3] has 63 asic
Chain[J4] has 63 asic
Chain[J1] has no freq in PIC, set default freq=550M
Chain[J1] has no core num in PIC
Chain[J3] has no freq in PIC, set default freq=550M
Chain[J3] has no core num in PIC
Chain[J4] has no freq in PIC, set default freq=550M
Chain[J4] has no core num in PIC
read PIC voltage=940 on chain[0]
Chain:0 chipnum=62
Chain[J1] voltage added=0.0V
Chain[J1] [minerMAC: 00:91:6b:66:c0:ed hashMAC: 00:00:00:00:00:00]
Chain:0 temp offset=0
Chain:0 base freq=100
Asic[ 0]:550
Asic[ 1]:550 Asic[ 2]:550 Asic[ 3]:550 Asic[ 4]:550 Asic[ 5]:550 Asic[ 6]:550 Asic[ 7]:550 Asic[ 8]:550
Asic[ 9]:550 Asic[10]:550 Asic[11]:550 Asic[12]:550 Asic[13]:550 Asic[14]:550 Asic[15]:550 Asic[16]:550
Asic[17]:550 Asic[18]:550 Asic[19]:550 Asic[20]:550 Asic[21]:550 Asic[22]:550 Asic[23]:550 Asic[24]:550
Asic[25]:550 Asic[26]:550 Asic[27]:550 Asic[28]:550 Asic[29]:550 Asic[30]:550 Asic[31]:550 Asic[32]:550
Asic[33]:550 Asic[34]:550 Asic[35]:550 Asic[36]:550 Asic[37]:550 Asic[38]:550 Asic[39]:550 Asic[40]:550
Asic[41]:550 Asic[42]:550 Asic[43]:550 Asic[44]:550 Asic[45]:550 Asic[46]:550 Asic[47]:550 Asic[48]:550
Asic[49]:550 Asic[50]:550 Asic[51]:550 Asic[52]:550 Asic[53]:550 Asic[54]:550 Asic[55]:550 Asic[56]:550
Asic[57]:550 Asic[58]:550 Asic[59]:550 Asic[60]:550 Asic[61]:550
Chain:0 max freq=550
Chain:0 min freq=550

read PIC voltage=940 on chain[2]
Chain:2 chipnum=63
Chain[J3] voltage added=0.0V
Chain[J3] [minerMAC: 00:91:6b:66:c0:ed hashMAC: 00:00:00:00:00:00]
Chain:2 temp offset=0
Chain:2 base freq=100
Asic[ 0]:550
Asic[ 1]:550 Asic[ 2]:550 Asic[ 3]:550 Asic[ 4]:550 Asic[ 5]:550 Asic[ 6]:550 Asic[ 7]:550 Asic[ 8]:550
Asic[ 9]:550 Asic[10]:550 Asic[11]:550 Asic[12]:550 Asic[13]:550 Asic[14]:550 Asic[15]:550 Asic[16]:550
Asic[17]:550 Asic[18]:550 Asic[19]:550 Asic[20]:550 Asic[21]:550 Asic[22]:550 Asic[23]:550 Asic[24]:550
Asic[25]:550 Asic[26]:550 Asic[27]:550 Asic[28]:550 Asic[29]:550 Asic[30]:550 Asic[31]:550 Asic[32]:550
Asic[33]:550 Asic[34]:550 Asic[35]:550 Asic[36]:550 Asic[37]:550 Asic[38]:550 Asic[39]:550 Asic[40]:550
Asic[41]:550 Asic[42]:550 Asic[43]:550 Asic[44]:550 Asic[45]:550 Asic[46]:550 Asic[47]:550 Asic[48]:550
Asic[49]:550 Asic[50]:550 Asic[51]:550 Asic[52]:550 Asic[53]:550 Asic[54]:550 Asic[55]:550 Asic[56]:550
Asic[57]:550 Asic[58]:550 Asic[59]:550 Asic[60]:550 Asic[61]:550 Asic[62]:550
Chain:2 max freq=550
Chain:2 min freq=550

read PIC voltage=940 on chain[3]
Chain:3 chipnum=63
Chain[J4] voltage added=0.0V
Chain[J4] [minerMAC: 00:91:6b:66:c0:ed hashMAC: 00:00:00:00:00:00]
Chain:3 temp offset=0
Chain:3 base freq=100
Asic[ 0]:550
Asic[ 1]:550 Asic[ 2]:550 Asic[ 3]:550 Asic[ 4]:550 Asic[ 5]:550 Asic[ 6]:550 Asic[ 7]:550 Asic[ 8]:550
Asic[ 9]:550 Asic[10]:550 Asic[11]:550 Asic[12]:550 Asic[13]:550 Asic[14]:550 Asic[15]:550 Asic[16]:550
Asic[17]:550 Asic[18]:550 Asic[19]:550 Asic[20]:550 Asic[21]:550 Asic[22]:550 Asic[23]:550 Asic[24]:550
Asic[25]:550 Asic[26]:550 Asic[27]:550 Asic[28]:550 Asic[29]:550 Asic[30]:550 Asic[31]:550 Asic[32]:550
Asic[33]:550 Asic[34]:550 Asic[35]:550 Asic[36]:550 Asic[37]:550 Asic[38]:550 Asic[39]:550 Asic[40]:550
Asic[41]:550 Asic[42]:550 Asic[43]:550 Asic[44]:550 Asic[45]:550 Asic[46]:550 Asic[47]:550 Asic[48]:550
Asic[49]:550 Asic[50]:550 Asic[51]:550 Asic[52]:550 Asic[53]:550 Asic[54]:550 Asic[55]:550 Asic[56]:550
Asic[57]:550 Asic[58]:550 Asic[59]:550 Asic[60]:550 Asic[61]:550 Asic[62]:550
Chain:3 max freq=550
Chain:3 min freq=550


Miner fix freq ...
read PIC voltage=940 on chain[0]
Chain:0 chipnum=62
Chain[J1] voltage added=0.0V
Chain[J1] [minerMAC: 00:91:6b:66:c0:ed hashMAC: 00:00:00:00:00:00]
Chain:0 temp offset=0
Chain:0 base freq=100
Asic[ 0]:550
Asic[ 1]:550 Asic[ 2]:550 Asic[ 3]:550 Asic[ 4]:550 Asic[ 5]:550 Asic[ 6]:550 Asic[ 7]:550 Asic[ 8]:550
Asic[ 9]:550 Asic[10]:550 Asic[11]:550 Asic[12]:550 Asic[13]:550 Asic[14]:550 Asic[15]:550 Asic[16]:550
Asic[17]:550 Asic[18]:550 Asic[19]:550 Asic[20]:550 Asic[21]:550 Asic[22]:550 Asic[23]:550 Asic[24]:550
Asic[25]:550 Asic[26]:550 Asic[27]:550 Asic[28]:550 Asic[29]:550 Asic[30]:550 Asic[31]:550 Asic[32]:550
Asic[33]:550 Asic[34]:550 Asic[35]:550 Asic[36]:550 Asic[37]:550 Asic[38]:550 Asic[39]:550 Asic[40]:550
Asic[41]:550 Asic[42]:550 Asic[43]:550 Asic[44]:550 Asic[45]:550 Asic[46]:550 Asic[47]:550 Asic[48]:550
Asic[49]:550 Asic[50]:550 Asic[51]:550 Asic[52]:550 Asic[53]:550 Asic[54]:550 Asic[55]:550 Asic[56]:550
Asic[57]:550 Asic[58]:550 Asic[59]:550 Asic[60]:550 Asic[61]:550
Chain:0 max freq=550
Chain:0 min freq=550

read PIC voltage=940 on chain[2]
Chain:2 chipnum=63
Chain[J3] voltage added=0.0V
Chain[J3] [minerMAC: 00:91:6b:66:c0:ed hashMAC: 00:00:00:00:00:00]
Chain:2 temp offset=0
Chain:2 base freq=100
Asic[ 0]:550
Asic[ 1]:550 Asic[ 2]:550 Asic[ 3]:550 Asic[ 4]:550 Asic[ 5]:550 Asic[ 6]:550 Asic[ 7]:550 Asic[ 8]:550
Asic[ 9]:550 Asic[10]:550 Asic[11]:550 Asic[12]:550 Asic[13]:550 Asic[14]:550 Asic[15]:550 Asic[16]:550
Asic[17]:550 Asic[18]:550 Asic[19]:550 Asic[20]:550 Asic[21]:550 Asic[22]:550 Asic[23]:550 Asic[24]:550
Asic[25]:550 Asic[26]:550 Asic[27]:550 Asic[28]:550 Asic[29]:550 Asic[30]:550 Asic[31]:550 Asic[32]:550
Asic[33]:550 Asic[34]:550 Asic[35]:550 Asic[36]:550 Asic[37]:550 Asic[38]:550 Asic[39]:550 Asic[40]:550
Asic[41]:550 Asic[42]:550 Asic[43]:550 Asic[44]:550 Asic[45]:550 Asic[46]:550 Asic[47]:550 Asic[48]:550
Asic[49]:550 Asic[50]:550 Asic[51]:550 Asic[52]:550 Asic[53]:550 Asic[54]:550 Asic[55]:550 Asic[56]:550
Asic[57]:550 Asic[58]:550 Asic[59]:550 Asic[60]:550 Asic[61]:550 Asic[62]:550
Chain:2 max freq=550
Chain:2 min freq=550

read PIC voltage=940 on chain[3]
Chain:3 chipnum=63
Chain[J4] voltage added=0.0V
Chain[J4] [minerMAC: 00:91:6b:66:c0:ed hashMAC: 00:00:00:00:00:00]
Chain:3 temp offset=0
Chain:3 base freq=100
Asic[ 0]:550
Asic[ 1]:550 Asic[ 2]:550 Asic[ 3]:550 Asic[ 4]:550 Asic[ 5]:550 Asic[ 6]:550 Asic[ 7]:550 Asic[ 8]:550
Asic[ 9]:550 Asic[10]:550 Asic[11]:550 Asic[12]:550 Asic[13]:550 Asic[14]:550 Asic[15]:550 Asic[16]:550
Asic[17]:550 Asic[18]:550 Asic[19]:550 Asic[20]:550 Asic[21]:550 Asic[22]:550 Asic[23]:550 Asic[24]:550
Asic[25]:550 Asic[26]:550 Asic[27]:550 Asic[28]:550 Asic[29]:550 Asic[30]:550 Asic[31]:550 Asic[32]:550
Asic[33]:550 Asic[34]:550 Asic[35]:550 Asic[36]:550 Asic[37]:550 Asic[38]:550 Asic[39]:550 Asic[40]:550
Asic[41]:550 Asic[42]:550 Asic[43]:550 Asic[44]:550 Asic[45]:550 Asic[46]:550 Asic[47]:550 Asic[48]:550
Asic[49]:550 Asic[50]:550 Asic[51]:550 Asic[52]:550 Asic[53]:550 Asic[54]:550 Asic[55]:550 Asic[56]:550
Asic[57]:550 Asic[58]:550 Asic[59]:550 Asic[60]:550 Asic[61]:550 Asic[62]:550
Chain:3 max freq=550
Chain:3 min freq=550

max freq = 550
prepare send works thread on chain[0]
prepare send works thread on chain[1]
prepare send works thread on chain[2]
prepare send works thread on chain[3]
prepare send works thread on chain[4]
prepare send works thread on chain[5]
prepare send works thread on chain[6]
prepare send works thread on chain[7]
prepare send works thread on chain[8]
prepare send works thread on chain[9]
prepare send works thread on chain[10]
prepare send works thread on chain[11]
prepare send works thread on chain[12]
prepare send works thread on chain[13]
prepare send works thread on chain[14]
prepare send works thread on chain[15]
Find hashboard on Chain[0]
Find hashboard on Chain[2]
Find hashboard on Chain[3]
use PIC voltage=940 on chain[0]
now set pic voltage=6 on chain[0]
use PIC voltage=940 on chain[2]
now set pic voltage=6 on chain[2]
use PIC voltage=940 on chain[3]
now set pic voltage=6 on chain[3]
enable_pic_dac on chain[0]
enable_pic_dac on chain[2]
enable_pic_dac on chain[3]
do 12 8xPatten test for 1 times
set command mode to VIL

initFpgaBoard: AsicType = 1387

initFpgaBoard: asicNum = 64

initFpgaBoard: real AsicNum = 63

--- check asic number
check chain[0]: asicNum = 63
check chain[2]: asicNum = 63
check chain[3]: asicNum = 63
Set Freq of PIC for Test Patten on Chain[0]

please disconnect chain 1 and power on miner without chain 1 maybe your problem solved.
after all your chain 1 hashboard need to repaired and only find 62 asic, that must be 63 asic.
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