..
I have now reworked a few things.
1. I supply the VDDIO_18 pin with 1.2V (using the chips power supply)
2. Checked if the crystal oscillator is still working with 1.2V and it is.
I did not look at your schematics, but you can (and should if you want to save cost) use Vcore for 1.2V. I have all my miners converted to 1.2V this way. Also you can make the 0.8V with a simple resistor divider from the Vcore (any voltage between 0.7V and 0.95V will work in my testing). The asic draws less than 10mA on the 0.8V line.
(edit glanced at the schematics..)
For testing i would tie the BI from the first asic to ground and the RI to 1.2V, so the asic will always respond to (correct) commands. If you are going to use level shifters between the asics (I think you need them if you use 1.2V as Vdd_IO, maybe not for 1.8V) you can skip level shifting the clock and just use a capacitor of 10nF.
(another edit)
Should the clock signal be available on the inverted CLK output pin of the ASIC? Because, I don't see anything there.
The clock must be present on the CLKO line.
Additionally, I'm powering the 4 ASICs with 2.4V because 2 of them are in parallel an then they are in series with the other 2. So, overall core voltage need to be 2.4V. But what I see is, that the voltage is not equally distributed over the ASICs. The first 2 ASICs have 0.8V and the bottom 2 are supplied with 1.6V.
If you do not have a level shifter on the NRST line you are keeping the 2nd asic reset, thus it will consume less power, resulting in unequal voltages over the domains.
I don't think debugging the circuit without voltage shifters will be easy. As long as you do not initialize the asics you should at least get a response on a read-register command, but anything more will be difficult.