Personal TRNG hardware prototype running in the lab (Single-Sided DIY edition).I am sharing the open-source files and PCB layouts for
Personal TRNG, an auditable DIY hardware entropy source built with an
ATmega328P and standard logic ICs designed for air-gapped security work.
Key Features- Entropy Source by Shutter System & Jitter Capture: Uses four independent 8 MHz crystals with a 74HC04 hex inverter and a 74HC74 dual D flip-flop to sample asynchronous jitter into the ATmega328P interrupts.
- Operating Modes: Features NRNG, TRNG, MRNG, and HRNG (combining hardware jitter with a 2D physics dice simulator: Decent Dice Web Simulator).
- Design & Output: Offered in single-sided and double-sided PCB editions (USB-C), streaming 115200 baud UART data with local 7-segment status feedback.
Why Hardware TRNG Matters for Sensitive Keys & Crypto WalletsA 256-bit private key or 24-word BIP-39 mnemonic only offers 256 bits of security if the underlying entropy source is genuinely unpredictable. When software wallets or closed-source devices rely on deterministic PRNGs, uninitialized buffers, or weak system clocks, the effective keyspace collapses—allowing attackers to precompute candidate seeds and sweep funds remotely without ever touching the user's device. Using an external, inspectable hardware TRNG separates entropy generation from general-purpose OS/firmware bugs and lets you verify the randomness pipeline yourself.
-- Wishing everyone peace of mind and concrete, truly unguessable cold-storage wallets after building and using Personal TRNG.RepositoriesNotesTreat output as raw entropy requiring offline KDF processing before key derivation. Released under an audit-only license. Community feedback and statistical testing (
ent,
Dieharder, NIST STS) are welcome.
Sample UART Telemetry & Audit Log (115200 Baud)For anyone auditing the firmware pipeline without building the hardware first, here is a live serial capture from the
TRNG mode showing the raw timer captures (
Block_J2 /
Block_J3), 4-bit XOR jitter windows across 8 entropy rounds, and the resulting 32-bit harvested block:
Sample UART Captured Process:Begin Random_Truly
Begin Block_Jitter
-> Jitter_Refresh <-
Begin Jitter_Strobe
-> Shutter_Chaos <-
11256~32823~18837~59648~37467~31241~1443~22986~9516~18239~3694~41168~35132~46998~18033~9288~49494~33382~7392~16161~42260~61096~46181~19911~10085~36840~26325~42342~52431~16331~31473~12416~
7088^14867^10999^4754^20529^14913^8485^3499^18673^20477^25693^12848^13674^16973^9745^6618^8488^3076^6436^37975^27159^8493^7235^26374^13657^29418^7009^11802^11184^2695^22173^4318^
End Jitter_Strobe
Begin True_Strobe
Block_J2(18): 33382 | Jitter_Window_2: 00000110
Block_J3(18): 3076 | Jitter_Window_3: 00000100
Jitter_Window (J2 xor J3): 00000010 -> Entropy_Round(1): 0010
End True_Strobe
...
Begin True_Strobe
Block_J2(25): 10085 | Jitter_Window_2: 00000101
Block_J3(25): 13657 | Jitter_Window_3: 00001001
Jitter_Window (J2 xor J3): 00001100 -> Entropy_Round(8): 1100
End True_Strobe
[_Harvested Block] 00100100011000110101011000011100 <- 610489884
End Block_Jitter
[_Magnitude Freed] 01001000110001101010110000111000 <- 1220979768
[_Magnitude Freed] 10010001100011010101100001110000 <- 2441959536
--------------------
Truly_ENTROPY: 294475888
Truly_RANDOM: 0.137126025
--------------------
End Random_Truly
--------------------
Truly_Rand_Range: 2.194016454
--------------------
T-RNG: 2
