We’re happy to announce a successful FPGA demo of our Scrypt ASIC, which will be available in August 2014. The FPGA prototype is a key step in our chip design verification and helps to confirm that our design works as expected. Also, it provides us critical insights into the actual performance of the real silicon before the chip is fabricated.
Setup:
We used a Wandboard Quad Freescale development board to control the Kintex-7 FPGA board via a wired SPI connection soldered to both boards. The Wandboard is running Ubuntu Linux and loaded with our device drivers for CPUMiner. For the demo, we started CPUMiner with the option to connect to a dedicated Scrypt mining pool with a low hashrate (~4MH/s) using a worker (fpga) in order to show earned shares in a reasonable amount of time, given that the FPGA hash rate is very low.
Results:
We achieved a hash rate of around 3.91kH/s on the FPGA. Since our FPGA is programmed with 1% of the number of cores and running at 1/12 the targeted clock frequency, the actual chip performance will be around 1,200x or around
4.7MH/s! We were also able to successfully mine about 188 shares during the 1.5 hours of setting up and filming. The payout will not be reflected in our account until the pool finds a valid block, which was about 3 days ago.
Overall, this test was a huge success and a key milestone for taping out and getting our design to production. Please visit our website (
www.blissdevices.com) to pre-order the Neon mining card which will feature 8 ASICs and deliver 37MH/s of hashing performance @ 180W.
See our video here:
https://www.youtube.com/watch?v=LLrQ40qUegg--Team Bliss
