[Group Buy #5] ASIC chip design funded by the people keep BTC decentralized

[Somekindabitcoin]

I'm going to follow this discussion. It seems like something really good is about to happen. Update me when it starts.

[Dagger75]

I'm very interested in this idea however; I can not afford to have someone just walk off w/ all my hard earned Bitcoin.  I think what others are saying too is that a basic business plan is needed since too many scammers in Crypto that are ruining it for the honest folks among us who want to get Rid of some of this Money-Grabbing Greed!!! 

Would be fabulous to have a extremely efficient 40nm ----> 28nm process chip that can be spread out among us Miners and NOT just have these ASIC companies hashing 75% of the entire network from the Chips WE all paid for w/ our 6-16 Month Pre-orders 

With a clear and intelligent plan along w/ investor $$ protection, I'm sure that you'll find 100's of us Miners willing to put in what BTC we can to support and, in the end, profit from this venture.

[Maidak]

I'm very interested in this idea however; I can not afford to have someone just walk off w/ all my hard earned Bitcoin.  I think what others are saying too is that a basic business plan is needed since too many scammers in Crypto that are ruining it for the honest folks among us who want to get Rid of some of this Money-Grabbing Greed!!! 

Would be fabulous to have a extremely efficient 40nm ----> 28nm process chip that can be spread out among us Miners and NOT just have these ASIC companies hashing 75% of the entire network from the Chips WE all paid for w/ our 6-16 Month Pre-orders 

With a clear and intelligent plan along w/ investor $$ protection, I'm sure that you'll find 100's of us Miners willing to put in what BTC we can to support and, in the end, profit from this venture.

Of course the OP will be edited with a proper plan layout. I want to hear opinions, suggestions, ideas get some brainstorming in this thread pros cons etc. before I write up any outline. I would not approach an idea if I was not confident in it. Currently I need to hear as much feedback on this as possible and maybe even a few PM's on people who would like to participate for what I see as a great idea that should of been turned reality as soon as we seen how BFL handled there very first ASIC chip. Obviously if they can some how manage this I see no reason why we don't and try to level the playing field just a tad? 

Who knows maybe Satoshi Nakamoto will be the one who holds the private key to the wallet with the funds for this type of project. What if just maybe you see that genesis block move around shortly after the proposal is written up.

Back to the topic I want this to be a community project and so far a great deal of positive feedback. How about the way you would like to see it work and move forward from the idea phase. Every post I read I will be taking to account as I work on the proposal.

[ZizzyDizzyMC]

If someone could give me the tools (software and knowledge) I'll gladly design an amazing chip.  I have designed 32bit PC's in minecraft so designing an asic can't be too hard.  That 32 Bit PC had 4MB ram and 10MB of storage.  (Of course i used a mod to help with it. It was RedPower mod made by Elorram. That mod added in most kinds of basic IC's like NAND and AND and NOR and OR and a few other basic chips.)

All I need to know is the basic chip design principles (In/Out/Work) and the software used to design such a chip. I have a (somewhat) good PC that should be able to run it (albeit slow).  I know it takes alot to manufacture a chip and boards but I'd at least like a shot at designing a chip. Be great practice for sure.

You can send me a pm if you have any info that I stated I would need.

[SebastianJu]

If someone could give me the tools (software and knowledge) I'll gladly design an amazing chip.  I have designed 32bit PC's in minecraft so designing an asic can't be too hard.  That 32 Bit PC had 4MB ram and 10MB of storage.  (Of course i used a mod to help with it. It was RedPower mod made by Elorram. That mod added in most kinds of basic IC's like NAND and AND and NOR and OR and a few other basic chips.)

All I need to know is the basic chip design principles (In/Out/Work) and the software used to design such a chip. I have a (somewhat) good PC that should be able to run it (albeit slow).  I know it takes alot to manufacture a chip and boards but I'd at least like a shot at designing a chip. Be great practice for sure.

You can send me a pm if you have any info that I stated I would need.

These tools costs very much money. Even renting them. And when you want something thats not really standard yet you need to work together with the software developer so they can fix every problem when it happens.

When i thought about creating 14nm Asic's with someone i called such a company by phone. Flowcad. And he spoke with the creator Cadence. Its not possible to simply buy such a product because the tech is not yet developed. That means you would have to sit together with TSMC, cadence and work together. Because the software isnt ready. The steps in between has to be finetuned all the way between all parts. He claimed its nothing like it was with 300nm once. There are no geometrical rules anymore. You have to have the rules not only in the last step, you need the rules all the time developing from the first step because the design has to be proofed from the start designing and is checked with every step done creating the design. Otherwise you could include your design into design software to check the foundry rules are applied. Thats not possible with low process nodes anymore. You need the software for developing.

Renting low process node development software costs 70,000€ - 80,000€ for a half year for analog and starts from 800,000€ for digital ASICs. Thats renting alone.

[cryptrol]

When i thought about creating 14nm Asic's with someone i called such a company by phone. Flowcad. And he spoke with the creator Cadence. Its not possible to simply buy such a product because the tech is not yet developed.

That's the point, the project development is a costly and risky business.
If your intention is to put the power to the small miners hands, then the best path is to go for a proven design with a good proven chip and make a monster buy order to reduce costs. Of course the community could help with the logistics involved and support requests from the buyers.

This could be done with kickstarter but considering that they take a (not so small) bite of the cake. It would be great to find a new decentralized platform to do it (like the one that is building Mike Hearn if I recall).

[mikerbiker6]

When i thought about creating 14nm Asic's with someone i called such a company by phone. Flowcad. And he spoke with the creator Cadence. Its not possible to simply buy such a product because the tech is not yet developed.

That's the point, the project development is a costly and risky business.
If your intention is to put the power to the small miners hands, then the best path is to go for a proven design with a good proven chip and make a monster buy order to reduce costs. Of course the community could help with the logistics involved and support requests from the buyers.

This could be done with kickstarter but considering that they take a (not so small) bite of the cake. It would be great to find a new decentralized platform to do it (like the one that is building Mike Hearn if I recall).

That is a good idea,
But which company do you choose?
Bitmain, spondoolies, seem like good companies but they will sell anyway.
So they have no motive to lower their price.

[zulover]

My 3 bits worth...
   

1. List what's available in regards to chip design already available open source and license ones .saves having to design c one from scratch. 

2. Choose one which will be best,  I.e. performance available once received from fab in a specific time frame e.g. a 28nm chip to be ready for 3 months needs to be at least a500ghs chip to give a machine which runs at least 10ths,most Likely a rackl system.

3.if step 2 is not good enough then step 1 should be too choose a node design and get a design made e.g 20nm or 18nm.

other possible steps contact designer manufacturer to get some quotes and time frames,bored designers, assemblers, software.

Working with the hive operation for boards would be a good idea it would save loads of time and money in the second phase of machine production because it's all done or in process. 

just a start...maybe.

[vs3]

Just my 2c -

yeah, it would be nice to have an open-source chip, but honestly - even if the design is open-sourced it still takes a lot of effort (read $$$) to turn chip design into a working silicone.

As this enterprise is going to require a lot of work there are 2 things that we need to clarify before we even start:
- engineering : design, software, development, etc - you need the appropriate people and resources for that. Do you have (at least some of) those?
- financials: there is no free soup. By the time you get a working chip there would be some expenses. How would they be recouped?

I guess all of this will be covered by The Plan.

And thinking about it - I guess we can start with simple questions like "where do we want to go" and "how do we get there".
The "where" part is somewhat clear - we want a chip (with some unknown specs so far).

[zulover]

Just my 2c -

yeah, it would be nice to have an open-source chip, but honestly - even if the design is open-sourced it still takes a lot of effort (read $$$) to turn chip design into a working silicone.

As this enterprise is going to require a lot of work there are 2 things that we need to clarify before we even start:
- engineering : design, software, development, etc - you need the appropriate people and resources for that. Do you have (at least some of) those?
- financials: there is no free soup. By the time you get a working chip there would be some expenses. How would they be recouped?

I guess all of this will be covered by The Plan.

And thinking about it - I guess we can start with simple questions like "where do we want to go" and "how do we get there".
The "where" part is somewhat clear - we want a chip (with some unknown specs so far).

+1

[Ramhound]

These tools costs very much money. Even renting them. And when you want something thats not really standard yet you need to work together with the software developer so they can fix every problem when it happens.

When i thought about creating 14nm Asic's with someone i called such a company by phone. Flowcad. And he spoke with the creator Cadence. Its not possible to simply buy such a product because the tech is not yet developed. That means you would have to sit together with TSMC, cadence and work together. Because the software isnt ready. The steps in between has to be finetuned all the way between all parts. He claimed its nothing like it was with 300nm once. There are no geometrical rules anymore. You have to have the rules not only in the last step, you need the rules all the time developing from the first step because the design has to be proofed from the start designing and is checked with every step done creating the design. Otherwise you could include your design into design software to check the foundry rules are applied. Thats not possible with low process nodes anymore. You need the software for developing.

Renting low process node development software costs 70,000€ - 80,000€ for a half year for analog and starts from 800,000€ for digital ASICs. Thats renting alone.

I have used software like Cadence in the past to design my own ICC in the past.  If the software isn't ready for 14nm, and the manufacturing process isn't even ready, then that more or less means we should look at manufacturing process that does have software ready.

In your research how is the software like Cadence licensed now that geometrical rules are no longer used.  My experience involved those rules, the software was easy enough to learn.  You started with the basic and worked your way up.  The major problem I see is unless you can spread the actual work around, have different design tasks, that this would be a ton of work for a small group of people.

What we have going for us is the fact we have an overal idea of the design itself.  We know how both SHA256 and SCRYPT.  All we have to do is figure out which ICCs ( AND, OR, NOT ) and in what combination to implement the design.  Everything we need to implement can be implemented using those three operations.

I forget the name of the software I used, it might have even been Cadence, this was back in 2008 and it ran on Linux.  The version of the software itself was note even current.  What we designed was actually manufactured at the end of the project.

[Ramhound]

If someone could give me the tools (software and knowledge) I'll gladly design an amazing chip.  I have designed 32bit PC's in minecraft so designing an asic can't be too hard.  That 32 Bit PC had 4MB ram and 10MB of storage.  (Of course i used a mod to help with it. It was RedPower mod made by Elorram. That mod added in most kinds of basic IC's like NAND and AND and NOR and OR and a few other basic chips.)

All I need to know is the basic chip design principles (In/Out/Work) and the software used to design such a chip. I have a (somewhat) good PC that should be able to run it (albeit slow).  I know it takes alot to manufacture a chip and boards but I'd at least like a shot at designing a chip. Be great practice for sure.

You can send me a pm if you have any info that I stated I would need.

Everything you did in Minecraft was simplified.

Here is a knowlege check: What are the three basic ICs that can implement any IC?

[TheRealSteve]

Here is a knowlege check: What are the three basic ICs that can implement any IC?

The 4001 and the 4011 - what do I win?
Wait.. you said three.. what do we need 3 for?

[Ramhound]

Here is a knowlege check: What are the three basic ICs that can implement any IC?

The 4001 and the 4011 - what do I win?
Wait.. you said three.. what do we need 3 for?

If you combine AND and OR with a NOT you get NAND and NOR.

One can extend that statement to say that NAND and NOR can represent any logic gate but the 3 basic logic gates are AND, OR, and NOT.

The reason I brought that up is the person made a big deal about XOR, XNOR, which again can created, by either NAND or NOR

[TheRealSteve]

awww, but you asked about ICs, not about logic gates *pout*

[SebastianJu]

These tools costs very much money. Even renting them. And when you want something thats not really standard yet you need to work together with the software developer so they can fix every problem when it happens.

When i thought about creating 14nm Asic's with someone i called such a company by phone. Flowcad. And he spoke with the creator Cadence. Its not possible to simply buy such a product because the tech is not yet developed. That means you would have to sit together with TSMC, cadence and work together. Because the software isnt ready. The steps in between has to be finetuned all the way between all parts. He claimed its nothing like it was with 300nm once. There are no geometrical rules anymore. You have to have the rules not only in the last step, you need the rules all the time developing from the first step because the design has to be proofed from the start designing and is checked with every step done creating the design. Otherwise you could include your design into design software to check the foundry rules are applied. Thats not possible with low process nodes anymore. You need the software for developing.

Renting low process node development software costs 70,000€ - 80,000€ for a half year for analog and starts from 800,000€ for digital ASICs. Thats renting alone.

I have used software like Cadence in the past to design my own ICC in the past.  If the software isn't ready for 14nm, and the manufacturing process isn't even ready, then that more or less means we should look at manufacturing process that does have software ready.

In your research how is the software like Cadence licensed now that geometrical rules are no longer used.  My experience involved those rules, the software was easy enough to learn.  You started with the basic and worked your way up.  The major problem I see is unless you can spread the actual work around, have different design tasks, that this would be a ton of work for a small group of people.

What we have going for us is the fact we have an overal idea of the design itself.  We know how both SHA256 and SCRYPT.  All we have to do is figure out which ICCs ( AND, OR, NOT ) and in what combination to implement the design.  Everything we need to implement can be implemented using those three operations.

I forget the name of the software I used, it might have even been Cadence, this was back in 2008 and it ran on Linux.  The version of the software itself was note even current.  What we designed was actually manufactured at the end of the project.

The geometrical rules are for the production process in the foundry. But with the last tech its somewhat more complicated since its not simple things like the minimum placeholder, the software has to simulate the production process with each step you do in the creating process because otherwise the materials could bring out unwanted results. At least thats how i understood it.

[Ramhound]

These tools costs very much money. Even renting them. And when you want something thats not really standard yet you need to work together with the software developer so they can fix every problem when it happens.

When i thought about creating 14nm Asic's with someone i called such a company by phone. Flowcad. And he spoke with the creator Cadence. Its not possible to simply buy such a product because the tech is not yet developed. That means you would have to sit together with TSMC, cadence and work together. Because the software isnt ready. The steps in between has to be finetuned all the way between all parts. He claimed its nothing like it was with 300nm once. There are no geometrical rules anymore. You have to have the rules not only in the last step, you need the rules all the time developing from the first step because the design has to be proofed from the start designing and is checked with every step done creating the design. Otherwise you could include your design into design software to check the foundry rules are applied. Thats not possible with low process nodes anymore. You need the software for developing.

Renting low process node development software costs 70,000€ - 80,000€ for a half year for analog and starts from 800,000€ for digital ASICs. Thats renting alone.

I have used software like Cadence in the past to design my own ICC in the past.  If the software isn't ready for 14nm, and the manufacturing process isn't even ready, then that more or less means we should look at manufacturing process that does have software ready.

In your research how is the software like Cadence licensed now that geometrical rules are no longer used.  My experience involved those rules, the software was easy enough to learn.  You started with the basic and worked your way up.  The major problem I see is unless you can spread the actual work around, have different design tasks, that this would be a ton of work for a small group of people.

What we have going for us is the fact we have an overal idea of the design itself.  We know how both SHA256 and SCRYPT.  All we have to do is figure out which ICCs ( AND, OR, NOT ) and in what combination to implement the design.  Everything we need to implement can be implemented using those three operations.

I forget the name of the software I used, it might have even been Cadence, this was back in 2008 and it ran on Linux.  The version of the software itself was note even current.  What we designed was actually manufactured at the end of the project.

The geometrical rules are for the production process in the foundry. But with the last tech its somewhat more complicated since its not simple things like the minimum placeholder, the software has to simulate the production process with each step you do in the creating process because otherwise the materials could bring out unwanted results. At least thats how i understood it.

What you are saying is that any software offered today requires rented time on actual hardware with minimum usage amounts?  That is going to be tough to work around.  The beauty of a project like this would have been to basically design the hardware in sections and a few key people putting it all together.

[Ramhound]

awww, but you asked about ICs, not about logic gates *pout*

I don't see a difference to be honest.

[crashoveride54902]

These tools costs very much money. Even renting them. And when you want something thats not really standard yet you need to work together with the software developer so they can fix every problem when it happens.

When i thought about creating 14nm Asic's with someone i called such a company by phone. Flowcad. And he spoke with the creator Cadence. Its not possible to simply buy such a product because the tech is not yet developed. That means you would have to sit together with TSMC, cadence and work together. Because the software isnt ready. The steps in between has to be finetuned all the way between all parts. He claimed its nothing like it was with 300nm once. There are no geometrical rules anymore. You have to have the rules not only in the last step, you need the rules all the time developing from the first step because the design has to be proofed from the start designing and is checked with every step done creating the design. Otherwise you could include your design into design software to check the foundry rules are applied. Thats not possible with low process nodes anymore. You need the software for developing.

Renting low process node development software costs 70,000€ - 80,000€ for a half year for analog and starts from 800,000€ for digital ASICs. Thats renting alone.

I have used software like Cadence in the past to design my own ICC in the past.  If the software isn't ready for 14nm, and the manufacturing process isn't even ready, then that more or less means we should look at manufacturing process that does have software ready.

In your research how is the software like Cadence licensed now that geometrical rules are no longer used.  My experience involved those rules, the software was easy enough to learn.  You started with the basic and worked your way up.  The major problem I see is unless you can spread the actual work around, have different design tasks, that this would be a ton of work for a small group of people.

What we have going for us is the fact we have an overal idea of the design itself.  We know how both SHA256 and SCRYPT.  All we have to do is figure out which ICCs ( AND, OR, NOT ) and in what combination to implement the design.  Everything we need to implement can be implemented using those three operations.

I forget the name of the software I used, it might have even been Cadence, this was back in 2008 and it ran on Linux.  The version of the software itself was note even current.  What we designed was actually manufactured at the end of the project.

The geometrical rules are for the production process in the foundry. But with the last tech its somewhat more complicated since its not simple things like the minimum placeholder, the software has to simulate the production process with each step you do in the creating process because otherwise the materials could bring out unwanted results. At least thats how i understood it.

What you are saying is that any software offered today requires rented time on actual hardware with minimum usage amounts?  That is going to be tough to work around.  The beauty of a project like this would have been to basically design the hardware in sections and a few key people putting it all together.

well what mm chip we aiming for? does it have to be the lowest? can't we start at a higher mm...maybe we'll get lucky n produce an even better chip

[zulover]

Yes of course doeant need to bw the lowest nm chip . Beacause a 40nm chip will have good power to hash ratio amdain thing well get it at cost.